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Added support for constant bit- or part-select for memory writes

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This commit is contained in:
Clifford Wolf 2014-07-17 13:13:21 +02:00
parent 1b00861d0a
commit 6d69d4aaa8
2 changed files with 56 additions and 9 deletions
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20
tests/simple/memory.v
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@ -114,3 +114,23 @@ assign rd_data = memory[rd_addr_buf];
endmodule
// ----------------------------------------------------------
module test05(clk, addr, wdata, rdata, wen);
input clk;
input [1:0] addr;
input [7:0] wdata;
output reg [7:0] rdata;
input [3:0] wen;
reg [7:0] mem [0:3];
integer i;
always @(posedge clk) begin
for (i = 0; i < 4; i = i+1)
if (wen[i]) mem[addr][i*2 +: 2] <= wdata[i*2 +: 2];
rdata <= mem[addr];
end
endmodule