Eddie Hung
1123c09588
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 19:39:12 -07:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp
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DSP inference for Xilinx (improved for ice40, initial support for ecp5)
2019-09-29 11:26:22 -07:00
Eddie Hung
f3e150d9a5
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 09:21:51 -07:00
Miodrag Milanović
ce0631c371
Merge pull request #1413 from YosysHQ/mmicko/backend_binary_out
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Support binary files for backends, fixes #1407
2019-09-29 10:37:34 +02:00
Eddie Hung
79b6edb639
Big rework; flop info now mostly in cells_sim.v
2019-09-28 23:48:17 -07:00
Miodrag Milanovic
0c380f0855
Add aiger and protobuf backends binary support
2019-09-28 09:51:48 +02:00
Miodrag Milanovic
d0493925ec
Support binary files for backends, fixes #1407
2019-09-28 09:36:18 +02:00
Eddie Hung
cfa6dd61ef
Use abc_mergeability attr for "r" extension
2019-09-27 18:41:43 -07:00
Eddie Hung
dc154c39a8
Fix infinite recursion
2019-09-27 17:45:49 -07:00
Eddie Hung
8f5710c464
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-27 15:14:31 -07:00
Aman Goel
5eebfabe42
Corrects btor2 backend
2019-09-27 12:40:17 -04:00
Eddie Hung
44374b1b2b
"abc_padding" attr for blackbox outputs that were padded, remove them later
2019-09-23 21:58:40 -07:00
Eddie Hung
c340fbfab2
Force $inout.out ports to begin with '$' to indicate internal
2019-09-23 21:58:04 -07:00
whitequark
4f426c2ac4
write_verilog: do not print (*init*) attributes on regs.
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If an init value is emitted for a reg, an (*init*) attribute is never
necessary, since it is exactly equivalent. On the other hand, some
tools that consume Verilog (ISE, Vivado, Quartus) complain about
(*init*) attributes because their interpretation differs from Yosys.
All (*init*) attributes that would not become reg init values anyway
are emitted as before.
2019-09-22 16:52:06 +00:00
Eddie Hung
2d9484c12c
When two boxes connect to each other, need not be a (* keep *)
2019-09-19 15:40:28 -07:00
Clifford Wolf
779ce3537f
Add "write_aiger -L"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-18 13:33:02 +02:00
Clifford Wolf
b88d2e5f30
Fix stupid bug in btor back-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-18 11:56:14 +02:00
Sean Cross
c1b628508d
backends: smt2: use $(CXX) variable for compiler
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The Makefile assumes the compiler is called `gcc`, which isn't always
true. In fact, if we're building on msys2 or msys2-64, the compiler
is called `i686-w64-mingw32-g++` or `x86_64-w64-mingw32-g++`.
Use the variable instead of hardcoding the name, to fix building on
these systems.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-09-08 15:47:09 +08:00
Eddie Hung
e9bb252e77
Recognise built-in types (e.g. $_DFF_*)
2019-08-30 20:15:09 -07:00
Eddie Hung
3247442bf9
Revert "Revert "Fix omode which inserts an output if none exists (otherwise abc9 breaks)""
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This reverts commit 8f0c1232d7
2019-08-28 17:34:00 -07:00
Eddie Hung
082a01954b
Revert "Output "h" extension only if boxes"
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This reverts commit 399ac760ff
2019-08-28 17:30:54 -07:00
Eddie Hung
399ac760ff
Output "h" extension only if boxes
2019-08-21 11:31:18 -07:00
Eddie Hung
8f0c1232d7
Revert "Fix omode which inserts an output if none exists (otherwise abc9 breaks)"
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This reverts commit 8182cb9d91
2019-08-21 11:29:40 -07:00
Eddie Hung
8182cb9d91
Fix omode which inserts an output if none exists (otherwise abc9 breaks)
2019-08-20 21:30:16 -07:00
Eddie Hung
4d123b7638
Revert "Only xaig if GetSize(output_bits) > 0"
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This reverts commit 7b646101e9
2019-08-20 21:22:38 -07:00
Eddie Hung
7b646101e9
Only xaig if GetSize(output_bits) > 0
2019-08-20 20:57:13 -07:00
Eddie Hung
f1a206ba03
Revert "Remove sequential extension"
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This reverts commit 091bf4a18b
2019-08-20 18:17:14 -07:00
Eddie Hung
091bf4a18b
Remove sequential extension
2019-08-20 18:16:37 -07:00
Eddie Hung
1b5d2de1d4
Do not sigmap!
2019-08-20 15:23:26 -07:00
Eddie Hung
c00d72cdb3
Minor refactor
2019-08-20 14:47:58 -07:00
Eddie Hung
45d4b33f0c
Output i/o/h extensions even if no boxes or flops
2019-08-19 13:17:31 -07:00
Eddie Hung
91687d3fea
Add (* abc_arrival *) attribute
2019-08-19 12:33:24 -07:00
Eddie Hung
2f4e0a5388
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-19 10:07:27 -07:00
Eddie Hung
10c69f71e9
Use %d
2019-08-19 09:16:20 -07:00
Eddie Hung
24c934f1af
Merge branch 'eddie/abc9_refactor' into xaig_dff
2019-08-16 16:51:22 -07:00
Eddie Hung
4fe307f1bc
Compute abc_scc_break and move CI/CO outside of each abc9
2019-08-16 15:41:17 -07:00
Clifford Wolf
0c5db07cd6
Fix various NDEBUG compiler warnings, closes #1255
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-13 13:29:03 +02:00
Clifford Wolf
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
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Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
Clifford Wolf
05c46a31dc
Merge pull request #1263 from ucb-bar/firrtl_err_on_unsupported_cell
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FIRRTL error on unsupported cell
2019-08-10 09:47:10 +02:00
Eddie Hung
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
Eddie Hung
7164996921
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
Eddie Hung
e6d5147214
Merge remote-tracking branch 'origin/master' into eddie/cleanup
2019-08-07 11:11:50 -07:00
Jim Lawson
5e8a98c8fd
Merge branch 'master' into firrtl_err_on_unsupported_cell
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# Conflicts:
# backends/firrtl/firrtl.cc
2019-08-07 10:14:45 -07:00
Eddie Hung
3090da2d98
Run "clean -purge" on holes_module in its own design
2019-08-07 09:54:27 -07:00
Clifford Wolf
48f7682e32
Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor
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Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
2019-08-07 12:31:32 +02:00
David Shah
dee8f61781
Merge pull request #1241 from YosysHQ/clifford/jsonfix
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Improved JSON attr/param encoding
2019-08-07 10:40:38 +01:00
Eddie Hung
e38f40af5b
Use IdString::begins_with()
2019-08-06 16:42:25 -07:00
Eddie Hung
a6bc9265fb
RTLIL::S{0,1} -> State::S{0,1}
2019-08-06 16:23:37 -07:00
Eddie Hung
046e1a5214
Use State::S{0,1}
2019-08-06 16:22:47 -07:00
Eddie Hung
3486235338
Make liberal use of IdString.in()
2019-08-06 16:18:18 -07:00
