mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
Remove sequential extension
This commit is contained in:
Eddie Hung
parent
bbab608691
commit
091bf4a18b
9 changed files with 68 additions and 730 deletions
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@ -76,32 +76,25 @@ void aiger_encode(std::ostream &f, int x)
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struct XAigerWriter
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{
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Module *module;
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bool zinit_mode;
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SigMap sigmap;
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dict<SigBit, bool> init_map;
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pool<SigBit> input_bits, output_bits;
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dict<SigBit, SigBit> not_map, ff_map, alias_map;
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dict<SigBit, SigBit> not_map, alias_map;
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits;
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vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits;
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vector<SigBit> ff_bits;
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dict<SigBit, float> arrival_times;
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vector<pair<int, int>> aig_gates;
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vector<int> aig_latchin, aig_latchinit, aig_outputs;
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vector<int> aig_outputs;
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int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
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dict<SigBit, int> aig_map;
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dict<SigBit, int> ordered_outputs;
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dict<SigBit, int> ordered_latches;
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vector<Cell*> box_list;
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bool omode = false;
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//dict<SigBit, int> init_inputs;
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//int initstate_ff = 0;
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int mkgate(int a0, int a1)
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{
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aig_m++, aig_a++;
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@ -144,7 +137,7 @@ struct XAigerWriter
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return a;
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}
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XAigerWriter(Module *module, bool zinit_mode, bool holes_mode=false) : module(module), zinit_mode(zinit_mode), sigmap(module)
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XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
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{
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pool<SigBit> undriven_bits;
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pool<SigBit> unused_bits;
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@ -167,14 +160,6 @@ struct XAigerWriter
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for (auto wire : module->wires())
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{
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if (wire->attributes.count("\\init")) {
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SigSpec initsig = sigmap(wire);
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Const initval = wire->attributes.at("\\init");
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for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
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if (initval[i] == State::S0 || initval[i] == State::S1)
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init_map[initsig[i]] = initval[i] == State::S1;
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}
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bool keep = wire->attributes.count("\\keep");
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for (int i = 0; i < GetSize(wire); i++)
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@ -218,12 +203,6 @@ struct XAigerWriter
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// box ordering, but not individual AIG cells
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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struct flop_data_t {
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IdString d_port;
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IdString q_port;
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int q_arrival;
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};
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dict<IdString, flop_data_t> flop_data;
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bool abc_box_seen = false;
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for (auto cell : module->selected_cells()) {
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@ -262,86 +241,25 @@ struct XAigerWriter
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log_assert(!holes_mode);
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if (cell->type == "$__ABC_FF_")
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{
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SigBit D = sigmap(cell->getPort("\\D").as_bit());
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SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
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unused_bits.erase(D);
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undriven_bits.erase(Q);
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alias_map[Q] = D;
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continue;
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}
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RTLIL::Module* inst_module = module->design->module(cell->type);
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if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
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abc_box_seen = true;
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toposort.node(cell->name);
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auto r = flop_data.insert(std::make_pair(cell->type, flop_data_t{IdString(), IdString(), 0}));
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if (r.second && inst_module->attributes.count("\\abc_flop")) {
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IdString &abc_flop_d = r.first->second.d_port;
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IdString &abc_flop_q = r.first->second.q_port;
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for (auto port_name : inst_module->ports) {
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auto wire = inst_module->wire(port_name);
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log_assert(wire);
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if (wire->attributes.count("\\abc_flop_d")) {
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if (abc_flop_d != IdString())
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log_error("More than one port has the 'abc_flop_d' attribute set on module '%s'.\n", log_id(cell->type));
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abc_flop_d = port_name;
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if (!holes_mode) {
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toposort.node(cell->name);
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for (const auto &conn : cell->connections()) {
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auto port_wire = inst_module->wire(conn.first);
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if (port_wire->port_input) {
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// Ignore inout for the sake of topographical ordering
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if (port_wire->port_output) continue;
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for (auto bit : sigmap(conn.second))
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bit_users[bit].insert(cell->name);
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}
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if (wire->attributes.count("\\abc_flop_q")) {
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if (abc_flop_q != IdString())
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log_error("More than one port has the 'abc_flop_q' attribute set on module '%s'.\n", log_id(cell->type));
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abc_flop_q = port_name;
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auto it = wire->attributes.find("\\abc_arrival");
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if (it != wire->attributes.end()) {
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if (it->second.flags != 0)
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log_error("Attribute 'abc_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(wire), log_id(cell->type));
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r.first->second.q_arrival = it->second.as_int();
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}
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}
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if (port_wire->port_output)
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for (auto bit : sigmap(conn.second))
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bit_drivers[bit].insert(cell->name);
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}
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if (abc_flop_d == IdString())
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log_error("'abc_flop_d' attribute not found on any ports on module '%s'.\n", log_id(cell->type));
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if (abc_flop_q == IdString())
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log_error("'abc_flop_q' attribute not found on any ports on module '%s'.\n", log_id(cell->type));
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}
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auto abc_flop_d = r.first->second.d_port;
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if (abc_flop_d != IdString()) {
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SigBit d = cell->getPort(abc_flop_d);
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SigBit I = sigmap(d);
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if (I != d)
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alias_map[I] = d;
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unused_bits.erase(d);
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auto abc_flop_q = r.first->second.q_port;
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SigBit q = cell->getPort(abc_flop_q);
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SigBit O = sigmap(q);
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if (O != q)
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alias_map[O] = q;
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undriven_bits.erase(O);
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ff_bits.emplace_back(q);
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auto arrival = r.first->second.q_arrival;
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if (arrival)
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arrival_times[q] = arrival;
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}
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for (const auto &conn : cell->connections()) {
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auto port_wire = inst_module->wire(conn.first);
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if (port_wire->port_input) {
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// Ignore inout for the sake of topographical ordering
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if (port_wire->port_output) continue;
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for (auto bit : sigmap(conn.second))
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bit_users[bit].insert(cell->name);
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}
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if (port_wire->port_output)
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for (auto bit : sigmap(conn.second))
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bit_drivers[bit].insert(cell->name);
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}
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}
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else {
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@ -548,7 +466,6 @@ struct XAigerWriter
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log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
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}
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init_map.sort();
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if (holes_mode) {
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struct sort_by_port_id {
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bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
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@ -564,7 +481,6 @@ struct XAigerWriter
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}
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not_map.sort();
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ff_map.sort();
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and_map.sort();
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aig_map[State::S0] = 0;
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@ -576,77 +492,12 @@ struct XAigerWriter
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aig_map[bit] = 2*aig_m;
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}
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for (auto bit : ff_bits) {
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aig_m++, aig_i++;
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log_assert(!aig_map.count(bit));
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aig_map[bit] = 2*aig_m;
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}
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dict<SigBit, int> ff_aig_map;
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for (auto &c : ci_bits) {
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RTLIL::SigBit bit = std::get<0>(c);
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aig_m++, aig_i++;
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auto r = aig_map.insert(std::make_pair(bit, 2*aig_m));
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if (!r.second)
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ff_aig_map[bit] = 2*aig_m;
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aig_map[bit] = 2*aig_m;
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}
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//if (zinit_mode)
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//{
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// for (auto it : ff_map) {
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// if (init_map.count(it.first))
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// continue;
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// aig_m++, aig_i++;
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// init_inputs[it.first] = 2*aig_m;
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// }
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//}
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//for (auto it : ff_map) {
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// aig_m++, aig_l++;
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// aig_map[it.first] = 2*aig_m;
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// ordered_latches[it.first] = aig_l-1;
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// if (init_map.count(it.first) == 0)
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// aig_latchinit.push_back(2);
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// else
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// aig_latchinit.push_back(init_map.at(it.first) ? 1 : 0);
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//}
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//if (!init_inputs.empty()) {
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// aig_m++, aig_l++;
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// initstate_ff = 2*aig_m+1;
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// aig_latchinit.push_back(0);
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//}
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//if (zinit_mode)
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//{
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// for (auto it : ff_map)
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// {
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// int l = ordered_latches[it.first];
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// if (aig_latchinit.at(l) == 1)
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// aig_map[it.first] ^= 1;
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// if (aig_latchinit.at(l) == 2)
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// {
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// int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
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// int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
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// aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
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// }
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// }
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//}
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//for (auto it : ff_map) {
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// int a = bit2aig(it.second);
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// int l = ordered_latches[it.first];
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// if (zinit_mode && aig_latchinit.at(l) == 1)
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// aig_latchin.push_back(a ^ 1);
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// else
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// aig_latchin.push_back(a);
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//}
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//if (!init_inputs.empty())
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// aig_latchin.push_back(1);
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for (auto &c : co_bits) {
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RTLIL::SigBit bit = std::get<0>(c);
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std::get<4>(c) = ordered_outputs[bit] = aig_o++;
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@ -658,11 +509,6 @@ struct XAigerWriter
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aig_outputs.push_back(bit2aig(bit));
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}
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for (auto bit : ff_bits) {
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aig_o++;
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aig_outputs.push_back(ff_aig_map.at(bit));
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}
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if (output_bits.empty()) {
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aig_o++;
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aig_outputs.push_back(0);
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@ -677,8 +523,6 @@ struct XAigerWriter
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int aig_obcjf = aig_obcj;
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log_assert(aig_m == aig_i + aig_l + aig_a);
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log_assert(aig_l == GetSize(aig_latchin));
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log_assert(aig_l == GetSize(aig_latchinit));
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log_assert(aig_obcjf == GetSize(aig_outputs));
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f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
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@ -689,15 +533,6 @@ struct XAigerWriter
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for (int i = 0; i < aig_i; i++)
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f << stringf("%d\n", 2*i+2);
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//for (int i = 0; i < aig_l; i++) {
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// if (zinit_mode || aig_latchinit.at(i) == 0)
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// f << stringf("%d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i));
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// else if (aig_latchinit.at(i) == 1)
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// f << stringf("%d %d 1\n", 2*(aig_i+i)+2, aig_latchin.at(i));
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// else if (aig_latchinit.at(i) == 2)
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// f << stringf("%d %d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i), 2*(aig_i+i)+2);
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//}
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for (int i = 0; i < aig_obc; i++)
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f << stringf("%d\n", aig_outputs.at(i));
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@ -715,15 +550,6 @@ struct XAigerWriter
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}
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else
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{
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//for (int i = 0; i < aig_l; i++) {
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// if (zinit_mode || aig_latchinit.at(i) == 0)
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// f << stringf("%d\n", aig_latchin.at(i));
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// else if (aig_latchinit.at(i) == 1)
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// f << stringf("%d 1\n", aig_latchin.at(i));
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// else if (aig_latchinit.at(i) == 2)
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// f << stringf("%d %d\n", aig_latchin.at(i), 2*(aig_i+i)+2);
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//}
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for (int i = 0; i < aig_obc; i++)
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f << stringf("%d\n", aig_outputs.at(i));
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@ -756,14 +582,14 @@ struct XAigerWriter
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std::stringstream h_buffer;
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auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
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write_h_buffer(1);
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log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ff_bits) + GetSize(ci_bits));
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write_h_buffer(input_bits.size() + ff_bits.size() + ci_bits.size());
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log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(ff_bits) + GetSize(co_bits));
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write_h_buffer(output_bits.size() + GetSize(ff_bits) + GetSize(co_bits));
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log_debug("piNum = %d\n", GetSize(input_bits) + GetSize(ff_bits));
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write_h_buffer(input_bits.size() + ff_bits.size());
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log_debug("poNum = %d\n", GetSize(output_bits) + GetSize(ff_bits));
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write_h_buffer(output_bits.size() + ff_bits.size());
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log_debug("ciNum = %d\n", GetSize(input_bits) + GetSize(ci_bits));
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write_h_buffer(input_bits.size() + ci_bits.size());
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log_debug("coNum = %d\n", GetSize(output_bits) + GetSize(co_bits));
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write_h_buffer(output_bits.size() + GetSize(co_bits));
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log_debug("piNum = %d\n", GetSize(input_bits));
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write_h_buffer(input_bits.size());
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log_debug("poNum = %d\n", GetSize(output_bits));
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write_h_buffer(output_bits.size());
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log_debug("boxNum = %d\n", GetSize(box_list));
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write_h_buffer(box_list.size());
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@ -779,7 +605,7 @@ struct XAigerWriter
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//for (auto bit : output_bits)
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// write_o_buffer(0);
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if (!box_list.empty() || !ff_bits.empty()) {
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if (!box_list.empty()) {
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RTLIL::Module *holes_module = module->design->addModule("$__holes__");
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log_assert(holes_module);
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@ -845,41 +671,13 @@ struct XAigerWriter
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std::stringstream r_buffer;
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auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
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log_debug("flopNum = %d\n", GetSize(ff_bits));
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write_r_buffer(ff_bits.size());
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int mergeability_class = 1;
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for (auto bit : ff_bits) {
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write_r_buffer(mergeability_class++);
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write_i_buffer(arrival_times.at(bit, 0));
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//write_o_buffer(0);
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}
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write_r_buffer(0);
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f << "r";
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std::string buffer_str = r_buffer.str();
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int32_t buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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std::stringstream s_buffer;
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auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
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write_s_buffer(ff_bits.size());
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for (auto bit : ff_bits) {
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auto it = bit.wire->attributes.find("\\init");
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if (it != bit.wire->attributes.end()) {
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auto init = it->second[bit.offset];
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if (init == RTLIL::S1) {
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write_s_buffer(1);
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continue;
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}
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}
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write_s_buffer(0);
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}
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f << "s";
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buffer_str = s_buffer.str();
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buffer_size_be = to_big_endian(buffer_str.size());
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f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
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f.write(buffer_str.data(), buffer_str.size());
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if (holes_module) {
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log_push();
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@ -915,7 +713,7 @@ struct XAigerWriter
|
|||
Pass::call(holes_design, "clean -purge");
|
||||
|
||||
std::stringstream a_buffer;
|
||||
XAigerWriter writer(holes_module, false /*zinit_mode*/, true /* holes_mode */);
|
||||
XAigerWriter writer(holes_module, true /* holes_mode */);
|
||||
writer.write_aiger(a_buffer, false /*ascii_mode*/);
|
||||
|
||||
delete holes_design;
|
||||
|
|
@ -953,9 +751,7 @@ struct XAigerWriter
|
|||
void write_map(std::ostream &f, bool verbose_map)
|
||||
{
|
||||
dict<int, string> input_lines;
|
||||
dict<int, string> init_lines;
|
||||
dict<int, string> output_lines;
|
||||
dict<int, string> latch_lines;
|
||||
dict<int, string> wire_lines;
|
||||
|
||||
for (auto wire : module->wires())
|
||||
|
|
@ -976,30 +772,10 @@ struct XAigerWriter
|
|||
|
||||
if (output_bits.count(b)) {
|
||||
int o = ordered_outputs.at(b);
|
||||
int init = 2;
|
||||
auto it = init_map.find(b);
|
||||
if (it != init_map.end())
|
||||
init = it->second ? 1 : 0;
|
||||
output_lines[o] += stringf("output %d %d %s %d\n", o - GetSize(co_bits), i, log_id(wire), init);
|
||||
output_lines[o] += stringf("output %d %d %s\n", o - GetSize(co_bits), i, log_id(wire));
|
||||
continue;
|
||||
}
|
||||
|
||||
//if (init_inputs.count(sig[i])) {
|
||||
// int a = init_inputs.at(sig[i]);
|
||||
// log_assert((a & 1) == 0);
|
||||
// init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
|
||||
// continue;
|
||||
//}
|
||||
|
||||
//if (ordered_latches.count(sig[i])) {
|
||||
// int l = ordered_latches.at(sig[i]);
|
||||
// if (zinit_mode && (aig_latchinit.at(l) == 1))
|
||||
// latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
|
||||
// else
|
||||
// latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
|
||||
// continue;
|
||||
//}
|
||||
|
||||
if (verbose_map) {
|
||||
if (aig_map.count(sig[i]) == 0)
|
||||
continue;
|
||||
|
|
@ -1015,10 +791,6 @@ struct XAigerWriter
|
|||
f << it.second;
|
||||
log_assert(input_lines.size() == input_bits.size());
|
||||
|
||||
init_lines.sort();
|
||||
for (auto &it : init_lines)
|
||||
f << it.second;
|
||||
|
||||
int box_count = 0;
|
||||
for (auto cell : box_list)
|
||||
f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
|
||||
|
|
@ -1030,10 +802,6 @@ struct XAigerWriter
|
|||
if (omode && output_bits.empty())
|
||||
f << "output " << output_lines.size() << " 0 $__dummy__\n";
|
||||
|
||||
latch_lines.sort();
|
||||
for (auto &it : latch_lines)
|
||||
f << it.second;
|
||||
|
||||
wire_lines.sort();
|
||||
for (auto &it : wire_lines)
|
||||
f << it.second;
|
||||
|
|
@ -1054,10 +822,6 @@ struct XAigerBackend : public Backend {
|
|||
log(" -ascii\n");
|
||||
log(" write ASCII version of AIGER format\n");
|
||||
log("\n");
|
||||
log(" -zinit\n");
|
||||
log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
|
||||
log(" uninitialized FFs.\n");
|
||||
log("\n");
|
||||
log(" -map <filename>\n");
|
||||
log(" write an extra file with port and latch symbols\n");
|
||||
log("\n");
|
||||
|
|
@ -1068,7 +832,6 @@ struct XAigerBackend : public Backend {
|
|||
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
{
|
||||
bool ascii_mode = false;
|
||||
bool zinit_mode = false;
|
||||
bool verbose_map = false;
|
||||
std::string map_filename;
|
||||
|
||||
|
|
@ -1081,10 +844,6 @@ struct XAigerBackend : public Backend {
|
|||
ascii_mode = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-zinit") {
|
||||
zinit_mode = true;
|
||||
continue;
|
||||
}
|
||||
if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
|
||||
map_filename = args[++argidx];
|
||||
continue;
|
||||
|
|
@ -1103,7 +862,7 @@ struct XAigerBackend : public Backend {
|
|||
if (top_module == nullptr)
|
||||
log_error("Can't find top module in current design!\n");
|
||||
|
||||
XAigerWriter writer(top_module, zinit_mode);
|
||||
XAigerWriter writer(top_module);
|
||||
writer.write_aiger(*f, ascii_mode);
|
||||
|
||||
if (!map_filename.empty()) {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue