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Merge pull request #1359 from YosysHQ/xc7dsp

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DSP inference for Xilinx (improved for ice40, initial support for ecp5)
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Eddie Hung 2019-09-29 11:26:22 -07:00 • committed by GitHub
commit 8474c5b366
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44 changed files with 6247 additions and 294 deletions
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16
backends/aiger/xaiger.cc
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@ -350,6 +350,8 @@ struct XAigerWriter
if (!box_module || !box_module->attributes.count("\\abc_box_id"))
continue;
bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
// Fully pad all unused input connections of this box cell with S0
// Fully pad all undriven output connections of this box cell with anonymous wires
// NB: Assume box_module->ports are sorted alphabetically
@ -394,7 +396,10 @@ struct XAigerWriter
rhs = it->second;
}
else {
rhs = module->addWire(NEW_ID, GetSize(w));
Wire *wire = module->addWire(NEW_ID, GetSize(w));
if (blackbox)
wire->set_bool_attribute(ID(abc_padding));
rhs = wire;
cell->setPort(port_name, rhs);
}
@ -405,12 +410,7 @@ struct XAigerWriter
if (O != b)
alias_map[O] = b;
undriven_bits.erase(O);
auto jt = input_bits.find(b);
if (jt != input_bits.end()) {
log_assert(keep_bits.count(O));
input_bits.erase(b);
}
input_bits.erase(b);
}
}
}
@ -429,7 +429,7 @@ struct XAigerWriter
// inherit existing inout's drivers
if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
|| keep_bits.count(bit)) {
RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str());
RTLIL::Wire *new_wire = module->wire(wire_name);
if (!new_wire)
new_wire = module->addWire(wire_name, GetSize(wire));