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Code Activity
yosys/backends
History
Eddie Hung 79b6edb639 Big rework; flop info now mostly in cells_sim.v
2019-09-28 23:48:17 -07:00
..
aiger Big rework; flop info now mostly in cells_sim.v 2019-09-28 23:48:17 -07:00
blif RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
btor Fix stupid bug in btor back-end 2019-09-18 11:56:14 +02:00
edif Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
firrtl Merge pull request #1258 from YosysHQ/eddie/cleanup 2019-08-10 09:52:14 +02:00
ilang RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
intersynth substr() -> compare() 2019-08-07 12:20:08 -07:00
json Implement improved JSON attr/param encoding 2019-08-01 12:34:52 +02:00
protobuf Support filename rewrite in backends 2019-06-18 14:39:52 -07:00
simplec Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 2019-08-06 04:47:55 +02:00
smt2 backends: smt2: use $(CXX) variable for compiler 2019-09-08 15:47:09 +08:00
smv substr() -> compare() 2019-08-07 12:20:08 -07:00
spice Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
table Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
verilog substr() -> compare() 2019-08-07 12:20:08 -07:00