| .. |
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aiger
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RTLIL::S{0,1} -> State::S{0,1}
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2019-08-06 16:23:37 -07:00 |
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blif
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RTLIL::S{0,1} -> State::S{0,1}
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2019-08-07 11:12:38 -07:00 |
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btor
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Use State::S{0,1}
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2019-08-06 16:22:47 -07:00 |
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edif
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Add "whitebox" attribute, add "read_verilog -wb"
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2019-04-18 17:45:47 +02:00 |
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firrtl
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Merge remote-tracking branch 'origin/master' into eddie/cleanup
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2019-08-07 11:11:50 -07:00 |
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ilang
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RTLIL::S{0,1} -> State::S{0,1}
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2019-08-07 11:12:38 -07:00 |
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intersynth
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RTLIL::S{0,1} -> State::S{0,1}
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2019-08-07 11:12:38 -07:00 |
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json
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Implement improved JSON attr/param encoding
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2019-08-01 12:34:52 +02:00 |
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protobuf
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Support filename rewrite in backends
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2019-06-18 14:39:52 -07:00 |
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simplec
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Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
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2019-08-06 04:47:55 +02:00 |
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smt2
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Make liberal use of IdString.in()
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2019-08-06 16:18:18 -07:00 |
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smv
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Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
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2019-08-06 04:47:55 +02:00 |
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spice
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Add "whitebox" attribute, add "read_verilog -wb"
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2019-04-18 17:45:47 +02:00 |
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table
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Add "whitebox" attribute, add "read_verilog -wb"
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2019-04-18 17:45:47 +02:00 |
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verilog
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RTLIL::S{0,1} -> State::S{0,1}
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2019-08-07 11:12:38 -07:00 |
