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https://github.com/YosysHQ/yosys
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Big rework; flop info now mostly in cells_sim.v
This commit is contained in:
Eddie Hung
parent
cfa6dd61ef
commit
79b6edb639
9 changed files with 500 additions and 456 deletions
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@ -81,11 +81,11 @@ struct XAigerWriter
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dict<SigBit, bool> init_map;
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pool<SigBit> input_bits, output_bits;
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dict<SigBit, SigBit> not_map, ff_map, alias_map;
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dict<SigBit, SigBit> not_map, /*ff_map,*/ alias_map;
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits;
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vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits;
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vector<std::pair<SigBit,int>> ff_bits;
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dict<SigBit, int> ff_bits;
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dict<SigBit, float> arrival_times;
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vector<pair<int, int>> aig_gates;
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@ -218,13 +218,8 @@ struct XAigerWriter
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// box ordering, but not individual AIG cells
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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struct flop_data_t {
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IdString d_port;
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IdString q_port;
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int q_arrival;
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};
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dict<IdString, flop_data_t> flop_data;
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bool abc_box_seen = false;
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std::vector<Cell*> flop_boxes;
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for (auto cell : module->selected_cells()) {
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if (cell->type == "$_NOT_")
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@ -269,6 +264,8 @@ struct XAigerWriter
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unused_bits.erase(D);
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undriven_bits.erase(Q);
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alias_map[Q] = D;
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auto r = ff_bits.insert(std::make_pair(D, 0));
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log_assert(r.second);
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continue;
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}
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@ -278,59 +275,6 @@ struct XAigerWriter
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toposort.node(cell->name);
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auto r = flop_data.insert(std::make_pair(cell->type, flop_data_t{IdString(), IdString(), 0}));
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if (r.second && inst_module->attributes.count("\\abc_flop")) {
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IdString &abc_flop_d = r.first->second.d_port;
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IdString &abc_flop_q = r.first->second.q_port;
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for (auto port_name : inst_module->ports) {
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auto wire = inst_module->wire(port_name);
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log_assert(wire);
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if (wire->attributes.count("\\abc_flop_d")) {
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if (abc_flop_d != IdString())
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log_error("More than one port has the 'abc_flop_d' attribute set on module '%s'.\n", log_id(cell->type));
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abc_flop_d = port_name;
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}
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if (wire->attributes.count("\\abc_flop_q")) {
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if (abc_flop_q != IdString())
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log_error("More than one port has the 'abc_flop_q' attribute set on module '%s'.\n", log_id(cell->type));
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abc_flop_q = port_name;
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auto it = wire->attributes.find("\\abc_arrival");
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if (it != wire->attributes.end()) {
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if (it->second.flags != 0)
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log_error("Attribute 'abc_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(wire), log_id(cell->type));
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r.first->second.q_arrival = it->second.as_int();
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}
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}
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}
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if (abc_flop_d == IdString())
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log_error("'abc_flop_d' attribute not found on any ports on module '%s'.\n", log_id(cell->type));
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if (abc_flop_q == IdString())
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log_error("'abc_flop_q' attribute not found on any ports on module '%s'.\n", log_id(cell->type));
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}
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auto abc_flop_d = r.first->second.d_port;
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if (abc_flop_d != IdString()) {
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SigBit d = cell->getPort(abc_flop_d);
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SigBit I = sigmap(d);
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if (I != d)
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alias_map[d] = I;
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unused_bits.erase(d);
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auto abc_flop_q = r.first->second.q_port;
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SigBit q = cell->getPort(abc_flop_q);
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log_assert(q == sigmap(q));
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undriven_bits.erase(q);
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auto it = cell->attributes.find(ID(abc_mergeability));
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log_assert(it != cell->attributes.end());
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ff_bits.emplace_back(q, it->second.as_int());
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cell->attributes.erase(it);
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auto arrival = r.first->second.q_arrival;
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if (arrival)
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arrival_times[q] = arrival;
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}
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for (const auto &conn : cell->connections()) {
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auto port_wire = inst_module->wire(conn.first);
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if (port_wire->port_input) {
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@ -345,6 +289,8 @@ struct XAigerWriter
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bit_drivers[bit].insert(cell->name);
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}
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if (inst_module->attributes.count("\\abc9_flop"))
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flop_boxes.push_back(cell);
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continue;
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}
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@ -403,6 +349,45 @@ struct XAigerWriter
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}
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if (abc_box_seen) {
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dict<IdString, std::pair<IdString,int>> flop_q;
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for (auto cell : flop_boxes) {
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auto r = flop_q.insert(std::make_pair(cell->type, std::make_pair(IdString(), 0)));
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SigBit d;
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if (r.second) {
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for (const auto &conn : cell->connections()) {
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const SigSpec &rhs = conn.second;
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if (!rhs.is_bit())
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continue;
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if (!ff_bits.count(rhs))
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continue;
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r.first->second.first = conn.first;
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Module *inst_module = module->design->module(cell->type);
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Wire *wire = inst_module->wire(conn.first);
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log_assert(wire);
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auto jt = wire->attributes.find("\\abc_arrival");
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if (jt != wire->attributes.end()) {
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if (jt->second.flags != 0)
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log_error("Attribute 'abc_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(wire), log_id(cell->type));
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r.first->second.second = jt->second.as_int();
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}
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d = rhs;
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log_assert(d == sigmap(d));
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break;
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}
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}
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else
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d = cell->getPort(r.first->second.first);
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auto it = cell->attributes.find(ID(abc9_mergeability));
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log_assert(it != cell->attributes.end());
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ff_bits.at(d) = it->second.as_int();
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cell->attributes.erase(it);
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auto arrival = r.first->second.second;
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if (arrival)
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arrival_times[d] = arrival;
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}
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for (auto &it : bit_users)
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if (bit_drivers.count(it.first))
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for (auto driver_cell : bit_drivers.at(it.first))
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@ -498,6 +483,29 @@ struct XAigerWriter
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}
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}
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}
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if (box_module->get_bool_attribute("\\abc9_flop")) {
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IdString port_name = "\\$currQ";
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RTLIL::Wire* w = box_module->wire(port_name);
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SigSpec rhs = cell->getPort(port_name);
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log_assert(GetSize(w) == GetSize(rhs));
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int offset = 0;
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for (auto b : rhs.bits()) {
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SigBit I = sigmap(b);
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if (b == RTLIL::Sx)
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b = State::S0;
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else if (I != b) {
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if (I == RTLIL::Sx)
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alias_map[b] = State::S0;
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else
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alias_map[b] = I;
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}
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co_bits.emplace_back(b, cell, port_name, offset++, 0);
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unused_bits.erase(b);
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}
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}
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box_list.emplace_back(cell);
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}
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@ -569,7 +577,7 @@ struct XAigerWriter
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}
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not_map.sort();
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ff_map.sort();
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//ff_map.sort();
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and_map.sort();
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aig_map[State::S0] = 0;
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@ -850,6 +858,28 @@ struct XAigerWriter
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}
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}
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if (box_module->get_bool_attribute("\\abc9_flop")) {
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log_assert(holes_cell);
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IdString port_name = "\\$currQ";
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Wire* w = box_module->wire(port_name);
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SigSpec rhs = cell->getPort(port_name);
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log_assert(GetSize(w) == GetSize(rhs));
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SigSpec port_wire;
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Wire *holes_wire;
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for (int i = 0; i < GetSize(w); i++) {
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box_inputs++;
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holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
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if (!holes_wire) {
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holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
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holes_wire->port_input = true;
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holes_wire->port_id = port_id++;
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holes_module->ports.push_back(holes_wire->name);
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}
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port_wire.append(holes_wire);
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}
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holes_cell->setPort(w->name, port_wire);
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}
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write_h_buffer(box_inputs);
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write_h_buffer(box_outputs);
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write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int());
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@ -861,6 +891,7 @@ struct XAigerWriter
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log_debug("flopNum = %d\n", GetSize(ff_bits));
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write_r_buffer(ff_bits.size());
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for (const auto &i : ff_bits) {
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log_assert(i.second > 0);
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write_r_buffer(i.second);
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const SigBit &bit = i.first;
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write_i_buffer(arrival_times.at(bit, 0));
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