2441 commits

Author	SHA1	Message	Date
Eddie Hung	3d577586fd	Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1	2019-04-10 16:15:23 -07:00
Eddie Hung	3f5dab0d09	Fix for when B_SIGNED = 1	2019-04-10 14:51:10 -07:00
Eddie Hung	32561332b2	Update doc for synth_xilinx	2019-04-10 14:48:58 -07:00
Eddie Hung	17a02df05c	ff_map.v after abc	2019-04-10 12:36:06 -07:00
Eddie Hung	1ec949d5ed	Tidy up	2019-04-10 09:02:42 -07:00
Eddie Hung	526aef9c2a	Move map_cells to before map_luts	2019-04-10 08:50:31 -07:00
Eddie Hung	e0b46eb4cb	WIP for $shiftx to wide mux	2019-04-10 08:49:55 -07:00
Eddie Hung	4dac9818bd	Update LUT delays	2019-04-10 08:49:39 -07:00
Eddie Hung	9a6da9a79a	synth_* with -retime option now calls abc with -D 1 as well	2019-04-10 08:32:53 -07:00
Eddie Hung	3e368593eb	Add cells.lut to techlibs/xilinx/	2019-04-09 14:33:37 -07:00
Eddie Hung	fd88ab5c83	synth_xilinx to call abc with -lut +/xilinx/cells.lut	2019-04-09 14:32:39 -07:00
Eddie Hung	b9e19071b8	Add delays to cells.box	2019-04-09 14:32:10 -07:00
Keith Rothman	e107ccdde8	Fix LUT6_2 definition. ... Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>	2019-04-09 11:43:19 -07:00
Eddie Hung	f2042fc7c4	synth_xilinx with abc9 to use -box	2019-04-09 11:01:46 -07:00
Eddie Hung	2ae26b986c	Add techlibs/xilinx/cells.box	2019-04-09 10:58:58 -07:00
Eddie Hung	3fc474aa73	Add support for synth_xilinx -abc9 and ignore abc9 -dress opt	2019-04-09 10:06:44 -07:00
Keith Rothman	5e0339855f	Add additional cells sim models for core 7-series primatives. ... Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>	2019-04-09 09:01:53 -07:00
Eddie Hung	bca3cf6843	Merge branch 'master' into xaig	2019-04-08 16:31:59 -07:00
Eddie Hung	1d526b7f06	Call shregmap twice -- once for variable, another for fixed	2019-04-05 17:35:49 -07:00
Eddie Hung	a5f33b5409	Move dffinit til after abc	2019-04-05 16:20:43 -07:00
Eddie Hung	0364a5d811	Merge branch 'eddie/fix_retime' into xc7srl	2019-04-05 15:46:18 -07:00
Eddie Hung	9758701574	Move techamp t:$_DFF_?N? to before abc call	2019-04-05 15:39:05 -07:00
Eddie Hung	23a6533e98	Retry	2019-04-05 15:31:54 -07:00
Eddie Hung	8b6085254a	Resolve @daveshah1 comment, update synth_xilinx help	2019-04-05 15:15:13 -07:00
Eddie Hung	ff0912c75e	synth_xilinx to techmap FFs after abc call, otherwise -retime fails	2019-04-05 14:43:06 -07:00
Eddie Hung	544843da71	techmap inside map_cells stage	2019-04-05 12:55:52 -07:00
Eddie Hung	7b7ddbdba7	Merge branch 'map_cells_before_map_luts' into xc7srl	2019-04-04 08:13:34 -07:00
Eddie Hung	e3f20b17af	Missing techmap entry in help	2019-04-04 08:13:10 -07:00
Eddie Hung	2fb02247a7	Use soft-logic, not LUT3 instantiation	2019-04-04 08:10:40 -07:00
Eddie Hung	572603409c	Merge branch 'map_cells_before_map_luts' into xc7srl	2019-04-04 07:54:42 -07:00
Eddie Hung	d9cb787391	synth_xilinx to map_cells before map_luts	2019-04-04 07:48:13 -07:00
Eddie Hung	77755b5a66	Cleanup comments	2019-04-04 07:41:40 -07:00
Eddie Hung	736e19f02d	t:$dff* -> t:$dff t:$dffe	2019-04-04 07:39:19 -07:00
Eddie Hung	0e2d929cea	-nosrl meant when -nobram	2019-04-03 08:28:07 -07:00
Eddie Hung	ff385a5ad0	Remove duplicate STARTUPE2	2019-04-03 08:14:09 -07:00
Eddie Hung	88630cd02c	Disable shregmap in synth_xilinx if -retime	2019-04-03 07:14:20 -07:00
Miodrag Milanovic	df92e9bdc2	Make nobram false by default for gowin	2019-04-02 19:21:01 +02:00
Eddie Hung	f9fb05cf66	synth_xilinx to use shregmap with -minlen 3	2019-03-25 13:18:55 -07:00
Eddie Hung	46753cf89f	Merge remote-tracking branch 'origin/master' into xc7srl	2019-03-22 13:10:42 -07:00
David Shah	46f6a60d58	xilinx: Add keep attribute where appropriate ... Signed-off-by: David Shah <dave@ds0.me>	2019-03-22 13:57:17 +00:00
Eddie Hung	4cc6b3e942	Add '-nosrl' option to synth_xilinx	2019-03-21 15:04:44 -07:00
Eddie Hung	81c207fb9b	Fine tune cells_map.v	2019-03-20 10:55:14 -07:00
Eddie Hung	505e4c2d59	Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length	2019-03-19 21:58:05 -07:00
Eddie Hung	5445cd4d00	Add support for variable length Xilinx SRL > 128	2019-03-19 17:44:33 -07:00
Eddie Hung	ae2a625d05	Restore original synth_xilinx commands	2019-03-19 16:14:08 -07:00
Eddie Hung	9156e18f92	Fix spacing	2019-03-19 16:12:32 -07:00
Eddie Hung	f239cb821e	Fix INIT for variable length SRs that have been bumped up one	2019-03-19 14:54:43 -07:00
Eddie Hung	24553326dd	Merge remote-tracking branch 'origin/master' into xc7srl	2019-03-19 13:11:30 -07:00
Clifford Wolf	fe1fb1336b	Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-19 20:30:28 +01:00
Eddie Hung	fadeadb8c8	Only accept <128 for variable length, only if $shiftx exclusive	2019-03-16 08:51:13 -07:00