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Tidy up

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This commit is contained in:
Eddie Hung 2019-04-10 09:02:42 -07:00
parent 526aef9c2a
commit 1ec949d5ed
1 changed files with 1 additions and 1 deletions
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2
techlibs/xilinx/cells_map.v
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@ -53,7 +53,7 @@ module \$shiftx (A, B, Y);
for (i = 0; i < B_WIDTH; i++)
if (i < num_mux8)
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
else if (i == num_mux8 && A_WIDTH > i*a_width0)
else if (i == num_mux8 && a_widthN > 0)
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH]));
else
assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}};