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synth_xilinx to call abc with -lut +/xilinx/cells.lut

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This commit is contained in:
Eddie Hung 2019-04-09 14:32:39 -07:00
parent b9e19071b8
commit fd88ab5c83
1 changed files with 2 additions and 2 deletions
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4
techlibs/xilinx/synth_xilinx.cc
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@ -276,9 +276,9 @@ struct SynthXilinxPass : public Pass
if (check_label(active, run_from, run_to, "map_luts"))
{
if (abc == "abc9")
Pass::call(design, abc + " -luts 2:2,3,6:5,10,20 -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
else
Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
Pass::call(design, abc + " -lut +/xilinx/cells.lut" + string(retime ? " -dff" : ""));
Pass::call(design, "clean");
Pass::call(design, "techmap -map +/xilinx/lut_map.v");
}