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Add cells.lut to techlibs/xilinx/

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This commit is contained in:
Eddie Hung 2019-04-09 14:33:37 -07:00
parent fd88ab5c83
commit 3e368593eb
2 changed files with 16 additions and 0 deletions
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1
techlibs/xilinx/Makefile.inc
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@ -31,6 +31,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.box))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.lut))
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))

15
techlibs/xilinx/cells.lut Normal file
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@ -0,0 +1,15 @@
# Max delays from https://pastebin.com/v2hrcksd
# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
# Since LUT delays are pushed onto the fabric as routing delays,
# assume each input costs +100ps
# K area delay
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