2441 commits

Author	SHA1	Message	Date
Eddie Hung	19b660ff6e	Fix SB_DFF comb model	2019-04-18 23:07:16 -07:00
Eddie Hung	0919f36b88	Missing close bracket	2019-04-18 17:50:11 -07:00
Eddie Hung	cf66416110	Annotate SB_DFF* with abc_flop and abc_box_id	2019-04-18 17:46:53 -07:00
Eddie Hung	ca1eb98a97	Add SB_DFF* to boxes	2019-04-18 17:46:32 -07:00
Eddie Hung	4c327cf316	Use new -wb flag for ABC flow	2019-04-18 10:32:41 -07:00
Eddie Hung	9278192efe	Also update Makefile.inc	2019-04-18 09:58:34 -07:00
Eddie Hung	7b6ab937c1	Make SB_LUT4 a blackbox	2019-04-18 09:05:22 -07:00
Eddie Hung	8024f41897	Fix rename	2019-04-18 09:04:34 -07:00
Eddie Hung	ed5e75ed7d	Rename to abc_*.{box,lut}	2019-04-18 09:02:58 -07:00
Eddie Hung	6008bb7002	Revert "synth_* with -retime option now calls abc with -D 1 as well" ... This reverts commit 9a6da9a79a.	2019-04-18 07:59:16 -07:00
Eddie Hung	0642baabbc	Merge branch 'master' into eddie/fix_retime	2019-04-18 07:57:17 -07:00
Eddie Hung	8fd455c910	Update Makefile.inc too	2019-04-17 15:19:48 -07:00
Eddie Hung	c795e14d25	Reduce to three devices: hx, lp, u	2019-04-17 15:19:02 -07:00
Eddie Hung	5c0853fc51	Add up5k timings	2019-04-17 15:10:39 -07:00
Eddie Hung	4b520ae627	Fix grammar	2019-04-17 15:10:22 -07:00
Eddie Hung	3105a8a653	Update error message	2019-04-17 15:07:44 -07:00
Eddie Hung	6f3e5297db	Add "-device" argument to synth_ice40	2019-04-17 15:04:46 -07:00
Eddie Hung	671cca59a9	Missing abc_flop_q attribute on SPRAM	2019-04-17 14:44:08 -07:00
Eddie Hung	437fec0d88	Map to SB_LUT4 from fastest input first	2019-04-17 13:01:17 -07:00
Eddie Hung	58847df1b9	Mark seq output ports with "abc_flop_q" attr	2019-04-17 12:27:45 -07:00
Eddie Hung	1eade06671	Also update Makefile.inc	2019-04-17 12:27:02 -07:00
Eddie Hung	4fb9ccfcd8	synth_ice40 to use renamed files	2019-04-17 12:22:03 -07:00
Eddie Hung	42c33db22c	Rename to abc.*	2019-04-17 12:15:34 -07:00
Eddie Hung	c1ebe51a75	Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues" ... This reverts commit a7632ab332.	2019-04-17 11:10:20 -07:00
Eddie Hung	a7632ab332	Try using an ICE40_CARRY_LUT primitive to avoid ABC issues	2019-04-17 11:10:04 -07:00
Eddie Hung	17fb6c3522	Fix spacing	2019-04-17 08:40:50 -07:00
Eddie Hung	743c164eee	Add SB_LUT4 to box library	2019-04-16 17:34:11 -07:00
Eddie Hung	7980118d74	Add ice40 box files	2019-04-16 16:39:30 -07:00
Eddie Hung	cbb85e40e8	Add MUXCY and XORCY to cells_box.v	2019-04-16 14:53:28 -07:00
Eddie Hung	aece97024d	Fix spacing	2019-04-16 13:16:20 -07:00
Eddie Hung	53b19ab1f5	Make cells.box whiteboxes not blackboxes	2019-04-16 12:43:14 -07:00
Eddie Hung	5189695362	read_verilog cells_box.v before techmap	2019-04-16 12:41:56 -07:00
Eddie Hung	d259e6dc14	synth_xilinx: before abc read +/xilinx/cells_box.v	2019-04-16 11:21:46 -07:00
Eddie Hung	3ac4977b70	Add +/xilinx/cells_box.v containing models for ABC boxes	2019-04-16 11:21:03 -07:00
Eddie Hung	8c6cf07acf	Revert "Add abc_box_id attribute to MUXF7/F8 cells" ... This reverts commit 8fbbd9b129.	2019-04-16 11:14:59 -07:00
Eddie Hung	8fbbd9b129	Add abc_box_id attribute to MUXF7/F8 cells	2019-04-15 22:25:09 -07:00
Eddie Hung	538592067e	Merge branch 'xaig' into xc7mux	2019-04-15 22:04:20 -07:00
Diego	f9272fc56d	GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow	2019-04-12 23:40:02 -05:00
Eddie Hung	04e466d5e4	Add support for synth_xilinx -abc9 and ignore abc9 -dress opt	2019-04-12 12:28:37 -07:00
Eddie Hung	f77da46a87	Merge remote-tracking branch 'origin/master' into xaig	2019-04-12 12:21:48 -07:00
Eddie Hung	db1a5ec6a2	Merge pull request #928 from litghost/add_xc7_sim_models ... Add additional cells sim models for core 7-series primitives.	2019-04-12 11:52:45 -07:00
Eddie Hung	8228b593ef	Merge remote-tracking branch 'origin/master' into xc7mux	2019-04-12 09:46:07 -07:00
Keith Rothman	1f9235ede5	Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra. ... Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>	2019-04-12 09:35:15 -07:00
Diego	643ae9bfc5	Fixing issues in CycloneV cell sim	2019-04-11 19:59:03 -05:00
Eddie Hung	233edf00fe	Fix cells_map.v some more	2019-04-11 10:48:14 -07:00
Eddie Hung	8658b56a08	More fine tuning	2019-04-11 10:08:05 -07:00
Eddie Hung	0ec8564099	Fix cells_map.v	2019-04-11 10:04:58 -07:00
Eddie Hung	bca3779657	Fix typo	2019-04-11 09:25:19 -07:00
Eddie Hung	87b8d29a90	Juggle opt calls in synth_xilinx	2019-04-11 09:13:39 -07:00
Eddie Hung	cd7b2de27f	WIP for cells_map.v -- maybe working?	2019-04-10 18:05:09 -07:00