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Only accept <128 for variable length, only if $shiftx exclusive

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Eddie Hung 2019-03-16 08:51:13 -07:00
parent 29a8d4745e
commit fadeadb8c8
2 changed files with 18 additions and 13 deletions
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6
techlibs/xilinx/cells_map.v
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@ -121,11 +121,7 @@ module \$__SHREG_ (input C, input D, input [31:0] L, input E, output Q);
else begin
// No way to create variable length shift registers >128 bits as Q31
// cannot be output to the fabric...
wire [DEPTH-1:-1] c;
genvar i;
for (i = 0; i < DEPTH; i=i+1)
\$__SHREG_ #(.DEPTH(1), .INIT(INIT_R[i]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl (.C(C), .D(c[i-1]), .L(0), .E(E), .Q(c[i]));
assign { c[-1], Q } = { D, c[L] };
wire _TECHMAP_FAIL_ = 1;
end
end
endgenerate