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80b92c7dd3
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change vcd output to have module contents under instance's name, more closely matching how it works in verilog
/ test (pull_request) Successful in 4m18s
/ test (push) Successful in 4m54s
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2026-03-26 18:21:14 -07:00 |
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2aa41137d4
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add simulator tests for queue()
/ test (pull_request) Successful in 7m59s
/ test (push) Successful in 5m3s
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2026-03-24 23:30:15 -07:00 |
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a0b2dc085c
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add test that simulator handles last-connect semantics properly
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2026-03-24 23:29:30 -07:00 |
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a8a541b357
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sim/compiler: fix registers so they properly retain their old value when not written
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2026-03-24 23:26:47 -07:00 |
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52c41bb5db
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display signals when panicking because not all inputs/outputs are written yet
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2026-03-24 23:25:14 -07:00 |
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a93e66d8ab
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update ui test's expected output for having rust-src available
/ test (pull_request) Successful in 4m20s
/ test (push) Successful in 4m57s
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2026-03-17 20:43:46 -07:00 |
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dbed947408
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change VCD id generation to be based on hashing the path, making them better for git diff
/ test (pull_request) Successful in 7m51s
/ test (push) Failing after 5m18s
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2026-02-23 20:05:10 -08:00 |
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cb4e1f42c0
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silence unused import warning
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2026-02-23 16:07:46 -08:00 |
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8c270b0e35
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silence warning for enums with only one variant
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2026-02-23 16:07:05 -08:00 |
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c632e5d570
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speed up simulation by optimizing SimulationImpl::read_traces
/ test (pull_request) Successful in 4m22s
/ test (push) Successful in 5m24s
this makes cpu/crates/cpu/tests/next_pc.rs take 56s instead of 168s
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2026-02-04 15:41:09 -08:00 |
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1bc835803b
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speed up LazyInterned by redoing caching using RwLock and add a thread-local cache
/ test (pull_request) Successful in 4m28s
/ test (push) Successful in 5m32s
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2026-02-03 18:00:36 -08:00 |
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9db3240644
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fix UI test's expected output
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2026-02-03 18:00:36 -08:00 |
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a96efa9696
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cache interned UInt/SInt types
/ test (pull_request) Successful in 4m8s
/ test (push) Successful in 4m44s
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2026-02-02 17:51:30 -08:00 |
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4ac1bcbc0a
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change Interner to use a sharded hash table
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2026-02-02 15:49:26 -08:00 |
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39810043ea
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move Interner into new mod interner
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2026-02-02 15:44:37 -08:00 |
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26b0dc3fd8
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change Interner to pub(crate)
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2026-02-02 15:42:12 -08:00 |
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11281a9842
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add a thread-local cache when using TypeIdMap
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2026-02-01 21:19:32 -08:00 |
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e366793204
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don't compare function pointers -- they're non-deterministic
/ test (pull_request) Successful in 4m5s
/ test (push) Successful in 4m36s
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2026-01-12 03:11:36 -08:00 |
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c97b44d9d6
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simplify SimValue Debug format, making complex structures much easier to read
/ test (pull_request) Successful in 3m55s
/ test (push) Successful in 4m30s
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2025-12-14 20:59:48 -08:00 |
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fbe4585578
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add FillInDefaultedGenerics<Type = Self> bound for SizeType
/ test (pull_request) Successful in 3m56s
/ test (push) Successful in 4m26s
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2025-12-10 20:10:39 -08:00 |
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9e803223d0
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support operations directly on SimValue, UIntValue, and SIntValue, and shared references to those
/ test (pull_request) Successful in 3m59s
/ test (push) Successful in 4m38s
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2025-11-24 00:14:53 -08:00 |
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2a65aa2bd5
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fix DynShr[SU]'s literal bits to properly shift right instead of left
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2025-11-20 02:25:05 -08:00 |
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2817cd3d58
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support Rust's default binding modes when destructuring with #[hdl(sim)] let/match
/ test (pull_request) Successful in 4m47s
/ test (push) Successful in 5m25s
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2025-11-14 00:20:54 -08:00 |
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053c1b2b10
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implement Display for SimValue<T>
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2025-11-14 00:20:54 -08:00 |
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17b58e8edb
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add utility impls for SimValue<ArrayType<_, _>>
/ test (pull_request) Successful in 4m52s
/ test (push) Successful in 5m28s
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2025-11-13 20:21:07 -08:00 |
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df020e9c9b
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add ExternModuleSimulatorState::read_past() and more output when simulator trace is enabled
/ test (pull_request) Successful in 4m52s
/ test (push) Successful in 5m28s
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2025-11-12 22:31:45 -08:00 |
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45fea70c18
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add ExternModuleSimulationState::fork_join_scope
/ test (pull_request) Successful in 4m47s
/ test (push) Successful in 5m24s
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2025-11-07 02:18:43 -08:00 |
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fbc8ffa5ae
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fix private fields in #[hdl] pub struct
/ test (pull_request) Successful in 4m53s
/ test (push) Successful in 5m38s
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2025-11-06 20:23:16 -08:00 |
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26a7090178
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add ParsedVisibility
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2025-11-06 20:22:53 -08:00 |
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0b77d1bea0
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fix Simulator panicking when you use PhantomConst
/ test (pull_request) Successful in 5m2s
/ test (push) Successful in 5m38s
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2025-11-05 22:44:43 -08:00 |
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840c5e1895
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add ExternModuleSimulationState::resettable helper for procedural simulations that have a reset input.
/ test (pull_request) Successful in 4m55s
/ test (push) Successful in 5m31s
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2025-11-03 23:59:36 -08:00 |
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c11a1743f9
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add sim.fork_join() and fix Simulator to handle running futures with arbitrary wakers
/ test (pull_request) Successful in 4m51s
/ test (push) Successful in 5m29s
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2025-10-30 21:16:05 -07:00 |
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0be9f9ce23
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fix JobGraph::run to not busy-wait
/ test (pull_request) Successful in 4m50s
/ test (push) Successful in 5m27s
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2025-10-27 22:57:12 -07:00 |
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0b82178740
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add PhantomConstGet to the known Type bounds for #[hdl] struct/enum
/ test (pull_request) Successful in 4m54s
/ test (push) Successful in 5m28s
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2025-10-27 20:08:22 -07:00 |
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4b24a88641
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add docs for #[hdl] and particularly for #[hdl] type aliases
/ test (pull_request) Successful in 4m50s
/ test (push) Successful in 5m26s
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2025-10-26 03:25:35 -07:00 |
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094c77e26e
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add #[hdl(get(|v| ...))] type GetStuff<P: PhantomConstGet<MyStruct>> = MyType or DynSize;
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2025-10-26 03:25:35 -07:00 |
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d2c8b023bf
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deny broken docs
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2025-10-26 03:25:35 -07:00 |
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edcc5927a5
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don't cache external job failures if they could be caused by the user killing processes
/ test (pull_request) Successful in 4m51s
/ test (push) Successful in 5m30s
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2025-10-24 02:27:20 -07:00 |
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7dc4417874
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add test_many_memories so we catch if memories are iterated in an inconsistent order like in 838bd469ce
/ test (pull_request) Successful in 4m44s
/ test (push) Successful in 5m22s
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2025-10-24 01:40:30 -07:00 |
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838bd469ce
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change SimulationImpl::trace_memories to a BTreeMap for consistent iteration order
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2025-10-24 00:53:13 -07:00 |
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b6e4cd0614
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move FormalMode to crate::testing and add to prelude
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2025-10-24 00:14:04 -07:00 |
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3e5b2f126a
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make UIntInRange[Inclusive][Type] castable from/to any UInt<N> and add methods to get bit_width, start, and end
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2025-10-23 23:52:41 -07:00 |
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b3cc28e2b6
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add transmit-only UART example
/ test (pull_request) Successful in 4m33s
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2025-10-22 20:11:02 -07:00 |
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26840daf13
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arty_a7: add divided clocks as available input peripherals so you're not stuck with 100MHz
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2025-10-22 20:11:02 -07:00 |
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c6feea6d51
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properly handle all XilinxAnnotations, this makes nextpnr-xilinx properly pick up the clock frequency
/ test (pull_request) Successful in 4m34s
/ test (push) Successful in 5m9s
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2025-10-21 22:24:02 -07:00 |
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409992961c
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switch to using verilog for reset synchronizer so we can use attributes on FDPE instances
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2025-10-21 22:24:02 -07:00 |
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2bdc8a7c72
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WIP adding xdc create_clock -- nextpnr-xilinx currently ignores it
/ test (pull_request) Successful in 4m35s
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2025-10-19 23:13:28 -07:00 |
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477a1f2d29
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Add peripherals and Arty A7 platforms -- blinky works correctly now on arty-a7-100t!
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2025-10-19 23:13:28 -07:00 |
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4d54f903be
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move vendor module to top level
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2025-10-17 15:00:19 -07:00 |
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3f5dd61e46
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WIP adding Platform
/ test (pull_request) Successful in 4m28s
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2025-10-17 05:55:22 -07:00 |
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