change VCD id generation to be based on hashing the path, making them better for git diff
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This commit is contained in:
Jacob Lifshay 2026-02-23 19:59:00 -08:00
parent cb4e1f42c0
commit dbed947408
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
28 changed files with 9183 additions and 8969 deletions

1
Cargo.lock generated
View file

@ -324,6 +324,7 @@ dependencies = [
"petgraph",
"serde",
"serde_json",
"sha2",
"tempfile",
"trybuild",
"vec_map",

View file

@ -31,6 +31,7 @@ ordered-float.workspace = true
petgraph.workspace = true
serde_json.workspace = true
serde.workspace = true
sha2.workspace = true
tempfile.workspace = true
vec_map.workspace = true
which.workspace = true

View file

@ -21,14 +21,30 @@ use crate::{
};
use bitvec::{order::Lsb0, slice::BitSlice};
use hashbrown::hash_map::Entry;
use sha2::{Digest, Sha256};
use std::{
collections::BTreeMap,
fmt::{self, Write as _},
io, mem,
};
#[derive(Default)]
#[derive(Default, Clone)]
struct PathHash(Sha256);
impl PathHash {
fn joined(mut self, segment: impl AsRef<[u8]>) -> Self {
let segment = segment.as_ref();
self.0.update(u32::to_le_bytes(
segment.len().try_into().expect("path segment is too big"),
));
self.0.update(segment);
self
}
}
struct Scope {
last_inserted: HashMap<Interned<str>, usize>,
path_hash: PathHash,
}
#[derive(Copy, Clone)]
@ -61,6 +77,13 @@ impl fmt::Display for VerilogIdentifier {
}
impl Scope {
fn new(path_hash: PathHash) -> Self {
Self {
last_inserted: Default::default(),
path_hash,
}
}
fn new_identifier(&mut self, unescaped_name: Interned<str>) -> VerilogIdentifier {
let next_disambiguator = match self.last_inserted.entry(unescaped_name) {
Entry::Vacant(entry) => {
@ -171,12 +194,10 @@ fn write_vcd_scope<W: io::Write, R>(
scope: &mut Scope,
f: impl FnOnce(&mut W, &mut Scope) -> io::Result<R>,
) -> io::Result<R> {
writeln!(
writer,
"$scope {scope_type} {} $end",
scope.new_identifier(scope_name),
)?;
let retval = f(writer, &mut Scope::default())?;
let path_hash = scope.path_hash.clone().joined(scope_name);
let scope_name = scope.new_identifier(scope_name);
writeln!(writer, "$scope {scope_type} {scope_name} $end")?;
let retval = f(writer, &mut Scope::new(path_hash))?;
writeln!(writer, "$upscope $end")?;
Ok(retval)
}
@ -291,19 +312,75 @@ impl WriteTrace for TraceScalar {
}
}
fn write_vcd_id<W: io::Write>(writer: &mut W, mut id: usize) -> io::Result<()> {
let min_char = b'!';
let max_char = b'~';
let base = (max_char - min_char + 1) as usize;
loop {
let digit = (id % base) as u8 + min_char;
id /= base;
writer.write_all(&[digit])?;
if id == 0 {
break;
#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
#[repr(transparent)]
struct VcdId(u64);
impl VcdId {
const CHAR_RANGE: std::ops::RangeInclusive<u8> = b'!'..=b'~';
const BASE: u8 = *Self::CHAR_RANGE.end() - *Self::CHAR_RANGE.start() + 1;
const LOW_HALF_CHARS: u32 = 5;
const LOW_HALF_MODULUS: u64 = (Self::BASE as u64).pow(Self::LOW_HALF_CHARS);
const fn from_str(s: &str) -> Option<Self> {
if s.is_empty() {
return None;
}
let mut retval = 0u64;
let mut bytes = s.as_bytes();
while let [ref rest @ .., digit] = *bytes {
bytes = rest;
let Some(digit) = digit.checked_sub(*Self::CHAR_RANGE.start()) else {
return None;
};
if digit >= Self::BASE {
return None;
}
let Some(v) = retval.checked_mul(Self::BASE as _) else {
return None;
};
let Some(v) = v.checked_add(digit as _) else {
return None;
};
retval = v;
}
Some(Self(retval))
}
Ok(())
#[must_use]
const fn write(self, out: &mut [u8]) -> usize {
let mut id = self.0;
let mut len = 0;
loop {
let digit = (id % Self::BASE as u64) as u8 + *Self::CHAR_RANGE.start();
id /= Self::BASE as u64;
if len < out.len() {
out[len] = digit;
}
len += 1;
if id == 0 {
break;
}
}
len
}
const MAX_ID_LEN: usize = Self(u64::MAX).write(&mut []);
}
/// check that VcdId properly round-trips
const _: () = {
let s = "RoundTrip";
let Some(id) = VcdId::from_str(s) else {
unreachable!();
};
let mut buf = [0u8; VcdId::MAX_ID_LEN];
let len = id.write(&mut buf);
assert!(crate::util::const_bytes_cmp(buf.split_at(len).0, s.as_bytes()).is_eq());
};
fn write_vcd_id<W: io::Write>(writer: &mut W, id: VcdId) -> io::Result<()> {
let mut buf = [0u8; VcdId::MAX_ID_LEN];
let len = id.write(&mut buf);
writer.write_all(&buf[..len])
}
struct Escaped<T: fmt::Display>(T);
@ -346,13 +423,16 @@ impl<T: fmt::Display> fmt::Display for Escaped<T> {
fn write_vcd_var<W: io::Write>(
properties: &mut VcdWriterProperties,
scope: &mut Scope,
memory_element_part_body: MemoryElementPartBody,
writer: &mut W,
var_type: &str,
size: usize,
location: TraceLocation,
name: VerilogIdentifier,
name: Interned<str>,
) -> io::Result<()> {
let path_hash = scope.path_hash.clone().joined(name);
let name = scope.new_identifier(name);
let id = match location {
TraceLocation::Scalar(id) => id.as_usize(),
TraceLocation::Memory(TraceMemoryLocation {
@ -384,6 +464,9 @@ fn write_vcd_var<W: io::Write>(
first_id + *element_index
}
};
let id = properties
.scalar_id_to_vcd_id_map
.builder_get_or_insert(id, &path_hash);
write!(writer, "$var {var_type} {size} ")?;
write_vcd_id(writer, id)?;
writeln!(writer, " {name} $end")
@ -414,12 +497,13 @@ impl WriteTrace for TraceUInt {
}
write_vcd_var(
properties,
scope,
MemoryElementPartBody::Scalar,
writer,
var_type,
ty.width(),
location,
scope.new_identifier(name),
name,
)
}
}
@ -494,12 +578,13 @@ impl WriteTrace for TraceEnumDiscriminant {
} = self;
write_vcd_var(
properties,
scope,
MemoryElementPartBody::EnumDiscriminant { ty },
writer,
"string",
1,
location,
scope.new_identifier(name),
name,
)
}
}
@ -569,12 +654,13 @@ impl WriteTrace for TracePhantomConst {
} = self;
write_vcd_var(
properties,
scope,
MemoryElementPartBody::Scalar,
writer,
"string",
1,
location,
scope.new_identifier(name),
name,
)
}
}
@ -596,12 +682,13 @@ impl WriteTrace for TraceSimOnly {
} = self;
write_vcd_var(
properties,
scope,
MemoryElementPartBody::Scalar,
writer,
"string",
1,
location,
scope.new_identifier(name),
name,
)
}
}
@ -923,6 +1010,9 @@ impl<W: io::Write> TraceWriterDecls for VcdWriterDecls<W> {
writeln!(writer, "$timescale {} $end", vcd_timescale(timescale))?;
let mut properties = VcdWriterProperties {
next_scalar_id: trace_scalar_id_count,
scalar_id_to_vcd_id_map: ScalarIdToVcdIdMapOrBuilder::Builder(
ScalarIdToVcdIdMapBuilder::default(),
),
memory_properties: (0..trace_memory_id_count)
.map(|_| MemoryProperties {
element_parts: Vec::with_capacity(8),
@ -935,9 +1025,16 @@ impl<W: io::Write> TraceWriterDecls for VcdWriterDecls<W> {
&mut writer,
ArgModule {
properties: &mut properties,
scope: &mut Scope::default(),
scope: &mut Scope::new(PathHash::default()),
},
)?;
let ScalarIdToVcdIdMapOrBuilder::Builder(scalar_id_to_vcd_id_map_builder) =
properties.scalar_id_to_vcd_id_map
else {
unreachable!();
};
properties.scalar_id_to_vcd_id_map =
ScalarIdToVcdIdMapOrBuilder::Built(scalar_id_to_vcd_id_map_builder.build());
writeln!(writer, "$enddefinitions $end")?;
writeln!(writer, "$dumpvars")?;
Ok(VcdWriter {
@ -967,8 +1064,88 @@ struct MemoryProperties {
element_index: usize,
}
struct ScalarIdToVcdIdMap {
scalar_id_to_vcd_id_map: Box<[VcdId]>,
}
#[derive(Default)]
struct ScalarIdToVcdIdMapBuilder {
scalar_id_to_vcd_id_map: BTreeMap<usize, VcdId>,
lower_half_to_next_upper_half_map: HashMap<u64, u64>,
}
impl ScalarIdToVcdIdMapBuilder {
/// `VcdId`s are based off of `path_hash` (and not `scalar_id`) since the hash doesn't change
/// when unrelated variables are added/removed, making the generated VCD more friendly for git diff.
fn get_or_insert(&mut self, scalar_id: usize, path_hash: &PathHash) -> VcdId {
*self
.scalar_id_to_vcd_id_map
.entry(scalar_id)
.or_insert_with(|| {
let hash = u128::from_le_bytes(
*path_hash
.0
.clone()
.finalize()
.first_chunk()
.expect("known to be bigger than u128"),
);
let lower_half = (hash % VcdId::LOW_HALF_MODULUS as u128) as u64;
let next_upper_half = self
.lower_half_to_next_upper_half_map
.entry(lower_half)
.or_insert(0);
let upper_half = *next_upper_half;
*next_upper_half += 1;
let Some(id) = upper_half
.checked_mul(VcdId::LOW_HALF_MODULUS)
.and_then(|v| v.checked_add(lower_half))
else {
panic!("too many VcdIds");
};
VcdId(id)
})
}
fn build(self) -> ScalarIdToVcdIdMap {
ScalarIdToVcdIdMap {
scalar_id_to_vcd_id_map: self
.scalar_id_to_vcd_id_map
.into_iter()
.enumerate()
.map(|(index, (scalar_id, vcd_id))| {
if index != scalar_id {
panic!("missing scalar id {index}");
}
vcd_id
})
.collect(),
}
}
}
enum ScalarIdToVcdIdMapOrBuilder {
Builder(ScalarIdToVcdIdMapBuilder),
Built(ScalarIdToVcdIdMap),
}
impl ScalarIdToVcdIdMapOrBuilder {
fn built_scalar_id_to_vcd_id(&self, scalar_id: usize) -> VcdId {
let Self::Built(v) = self else {
panic!("ScalarIdToVcdIdMap isn't built yet");
};
v.scalar_id_to_vcd_id_map[scalar_id]
}
fn builder_get_or_insert(&mut self, scalar_id: usize, path_hash: &PathHash) -> VcdId {
let Self::Builder(v) = self else {
panic!("ScalarIdToVcdIdMap is already built");
};
v.get_or_insert(scalar_id, path_hash)
}
}
struct VcdWriterProperties {
next_scalar_id: usize,
scalar_id_to_vcd_id_map: ScalarIdToVcdIdMapOrBuilder,
memory_properties: Box<[MemoryProperties]>,
}
@ -988,7 +1165,7 @@ impl<W: io::Write + 'static> VcdWriter<W> {
fn write_string_value_change(
writer: &mut impl io::Write,
value: impl fmt::Display,
id: usize,
id: VcdId,
) -> io::Result<()> {
write!(writer, "s{} ", Escaped(value))?;
write_vcd_id(writer, id)?;
@ -998,7 +1175,7 @@ fn write_string_value_change(
fn write_bits_value_change(
writer: &mut impl io::Write,
value: &BitSlice,
id: usize,
id: VcdId,
) -> io::Result<()> {
match value.len() {
0 => writer.write_all(b"s0 ")?,
@ -1028,7 +1205,7 @@ fn write_enum_discriminant_value_change(
writer: &mut impl io::Write,
variant_index: usize,
ty: Enum,
id: usize,
id: VcdId,
) -> io::Result<()> {
write_string_value_change(
writer,
@ -1063,7 +1240,9 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
MemoryElementPartBody::Scalar => write_bits_value_change(
&mut self.writer,
&element_data[start..start + len],
first_id + element_index,
self.properties
.scalar_id_to_vcd_id_map
.built_scalar_id_to_vcd_id(first_id + element_index),
)?,
MemoryElementPartBody::EnumDiscriminant { ty } => {
let mut variant_index = 0;
@ -1073,7 +1252,9 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
&mut self.writer,
variant_index,
*ty,
first_id + element_index,
self.properties
.scalar_id_to_vcd_id_map
.built_scalar_id_to_vcd_id(first_id + element_index),
)?
}
}
@ -1082,11 +1263,23 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
}
fn set_signal_uint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
write_bits_value_change(&mut self.writer, value, id.as_usize())
write_bits_value_change(
&mut self.writer,
value,
self.properties
.scalar_id_to_vcd_id_map
.built_scalar_id_to_vcd_id(id.as_usize()),
)
}
fn set_signal_sint(&mut self, id: TraceScalarId, value: &BitSlice) -> Result<(), Self::Error> {
write_bits_value_change(&mut self.writer, value, id.as_usize())
write_bits_value_change(
&mut self.writer,
value,
self.properties
.scalar_id_to_vcd_id_map
.built_scalar_id_to_vcd_id(id.as_usize()),
)
}
fn finish_init(&mut self) -> Result<(), Self::Error> {
@ -1118,7 +1311,14 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
variant_index: usize,
ty: Enum,
) -> Result<(), Self::Error> {
write_enum_discriminant_value_change(&mut self.writer, variant_index, ty, id.as_usize())
write_enum_discriminant_value_change(
&mut self.writer,
variant_index,
ty,
self.properties
.scalar_id_to_vcd_id_map
.built_scalar_id_to_vcd_id(id.as_usize()),
)
}
fn set_signal_phantom_const(
@ -1128,7 +1328,13 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
) -> Result<(), Self::Error> {
// avoid multi-line strings because GTKWave can't display them properly:
// https://github.com/gtkwave/gtkwave/issues/460
write_string_value_change(&mut self.writer, format_args!("{ty:?}"), id.as_usize())
write_string_value_change(
&mut self.writer,
format_args!("{ty:?}"),
self.properties
.scalar_id_to_vcd_id_map
.built_scalar_id_to_vcd_id(id.as_usize()),
)
}
fn set_signal_sim_only_value(
@ -1136,7 +1342,13 @@ impl<W: io::Write> TraceWriter for VcdWriter<W> {
id: TraceScalarId,
value: &DynSimOnlyValue,
) -> Result<(), Self::Error> {
write_string_value_change(&mut self.writer, format_args!("{value:?}"), id.as_usize())
write_string_value_change(
&mut self.writer,
format_args!("{value:?}"),
self.properties
.scalar_id_to_vcd_id_map
.built_scalar_id_to_vcd_id(id.as_usize()),
)
}
}
@ -1161,7 +1373,7 @@ mod tests {
#[test]
fn test_scope() {
let mut scope = Scope::default();
let mut scope = Scope::new(PathHash::default());
assert_eq!(&*scope.new_identifier("foo".intern()).unescaped_name, "foo");
assert_eq!(
&*scope.new_identifier("foo_0".intern()).unescaped_name,

View file

@ -1,283 +1,283 @@
$timescale 1 ps $end
$scope module array_rw $end
$scope struct array_in $end
$var wire 8 ! \[0] $end
$var wire 8 " \[1] $end
$var wire 8 # \[2] $end
$var wire 8 $ \[3] $end
$var wire 8 % \[4] $end
$var wire 8 & \[5] $end
$var wire 8 ' \[6] $end
$var wire 8 ( \[7] $end
$var wire 8 ) \[8] $end
$var wire 8 * \[9] $end
$var wire 8 + \[10] $end
$var wire 8 , \[11] $end
$var wire 8 - \[12] $end
$var wire 8 . \[13] $end
$var wire 8 / \[14] $end
$var wire 8 0 \[15] $end
$var wire 8 Yvfu^ \[0] $end
$var wire 8 |Cs`W \[1] $end
$var wire 8 M!nsb \[2] $end
$var wire 8 59L{w \[3] $end
$var wire 8 o2+|F \[4] $end
$var wire 8 ikzV5 \[5] $end
$var wire 8 [E$Z* \[6] $end
$var wire 8 ?"~01 \[7] $end
$var wire 8 /kghT \[8] $end
$var wire 8 +}(9) \[9] $end
$var wire 8 iMP}= \[10] $end
$var wire 8 2M0tL \[11] $end
$var wire 8 :AjkA \[12] $end
$var wire 8 VM_:8 \[13] $end
$var wire 8 UveL2 \[14] $end
$var wire 8 A)9Z6 \[15] $end
$upscope $end
$scope struct array_out $end
$var wire 8 1 \[0] $end
$var wire 8 2 \[1] $end
$var wire 8 3 \[2] $end
$var wire 8 4 \[3] $end
$var wire 8 5 \[4] $end
$var wire 8 6 \[5] $end
$var wire 8 7 \[6] $end
$var wire 8 8 \[7] $end
$var wire 8 9 \[8] $end
$var wire 8 : \[9] $end
$var wire 8 ; \[10] $end
$var wire 8 < \[11] $end
$var wire 8 = \[12] $end
$var wire 8 > \[13] $end
$var wire 8 ? \[14] $end
$var wire 8 @ \[15] $end
$var wire 8 2zdj1 \[0] $end
$var wire 8 =;m_[ \[1] $end
$var wire 8 @9Hd \[2] $end
$var wire 8 C:="| \[3] $end
$var wire 8 IDk7# \[4] $end
$var wire 8 i]E1i \[5] $end
$var wire 8 tK,M] \[6] $end
$var wire 8 tGp!\ \[7] $end
$var wire 8 ."qjK \[8] $end
$var wire 8 AUO:R \[9] $end
$var wire 8 'kx`n \[10] $end
$var wire 8 U&(K\ \[11] $end
$var wire 8 q<O41 \[12] $end
$var wire 8 zvj)] \[13] $end
$var wire 8 >0H<( \[14] $end
$var wire 8 ARhXJ \[15] $end
$upscope $end
$var wire 8 A read_index $end
$var wire 8 B read_data $end
$var wire 8 C write_index $end
$var wire 8 D write_data $end
$var wire 1 E write_en $end
$var wire 8 -n:7@ read_index $end
$var wire 8 >h<=Z read_data $end
$var wire 8 [xld3 write_index $end
$var wire 8 J+DYh write_data $end
$var wire 1 z,@WW write_en $end
$scope struct array_wire $end
$var wire 8 F \[0] $end
$var wire 8 G \[1] $end
$var wire 8 H \[2] $end
$var wire 8 I \[3] $end
$var wire 8 J \[4] $end
$var wire 8 K \[5] $end
$var wire 8 L \[6] $end
$var wire 8 M \[7] $end
$var wire 8 N \[8] $end
$var wire 8 O \[9] $end
$var wire 8 P \[10] $end
$var wire 8 Q \[11] $end
$var wire 8 R \[12] $end
$var wire 8 S \[13] $end
$var wire 8 T \[14] $end
$var wire 8 U \[15] $end
$var wire 8 B{KJS \[0] $end
$var wire 8 V'K*& \[1] $end
$var wire 8 4zI$O \[2] $end
$var wire 8 %TTk[ \[3] $end
$var wire 8 IgSeY \[4] $end
$var wire 8 &&1T" \[5] $end
$var wire 8 5)-l\ \[6] $end
$var wire 8 0RsLb \[7] $end
$var wire 8 T>:}D \[8] $end
$var wire 8 DPpZ* \[9] $end
$var wire 8 %E(nf \[10] $end
$var wire 8 2'pba \[11] $end
$var wire 8 e/c1: \[12] $end
$var wire 8 ;w.C7 \[13] $end
$var wire 8 fwdfu \[14] $end
$var wire 8 *R\vx \[15] $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
b11111111 !
b1111111 "
b111111 #
b11111 $
b1111 %
b111 &
b11 '
b1 (
b0 )
b10000000 *
b11000000 +
b11100000 ,
b11110000 -
b11111000 .
b11111100 /
b11111110 0
b11111111 1
b1111111 2
b111111 3
b11111 4
b1111 5
b111 6
b11 7
b1 8
b0 9
b10000000 :
b11000000 ;
b11100000 <
b11110000 =
b11111000 >
b11111100 ?
b11111110 @
b0 A
b11111111 B
b0 C
b0 D
0E
b11111111 F
b1111111 G
b111111 H
b11111 I
b1111 J
b111 K
b11 L
b1 M
b0 N
b10000000 O
b11000000 P
b11100000 Q
b11110000 R
b11111000 S
b11111100 T
b11111110 U
b11111111 Yvfu^
b1111111 |Cs`W
b111111 M!nsb
b11111 59L{w
b1111 o2+|F
b111 ikzV5
b11 [E$Z*
b1 ?"~01
b0 /kghT
b10000000 +}(9)
b11000000 iMP}=
b11100000 2M0tL
b11110000 :AjkA
b11111000 VM_:8
b11111100 UveL2
b11111110 A)9Z6
b11111111 2zdj1
b1111111 =;m_[
b111111 @9Hd
b11111 C:="|
b1111 IDk7#
b111 i]E1i
b11 tK,M]
b1 tGp!\
b0 ."qjK
b10000000 AUO:R
b11000000 'kx`n
b11100000 U&(K\
b11110000 q<O41
b11111000 zvj)]
b11111100 >0H<(
b11111110 ARhXJ
b0 -n:7@
b11111111 >h<=Z
b0 [xld3
b0 J+DYh
0z,@WW
b11111111 B{KJS
b1111111 V'K*&
b111111 4zI$O
b11111 %TTk[
b1111 IgSeY
b111 &&1T"
b11 5)-l\
b1 0RsLb
b0 T>:}D
b10000000 DPpZ*
b11000000 %E(nf
b11100000 2'pba
b11110000 e/c1:
b11111000 ;w.C7
b11111100 fwdfu
b11111110 *R\vx
$end
#1000000
b1 A
b1111111 B
b1 -n:7@
b1111111 >h<=Z
#2000000
b10 A
b111111 B
b10 -n:7@
b111111 >h<=Z
#3000000
b11 A
b11111 B
b11 -n:7@
b11111 >h<=Z
#4000000
b100 A
b1111 B
b100 -n:7@
b1111 >h<=Z
#5000000
b101 A
b111 B
b101 -n:7@
b111 >h<=Z
#6000000
b110 A
b11 B
b110 -n:7@
b11 >h<=Z
#7000000
b111 A
b1 B
b111 -n:7@
b1 >h<=Z
#8000000
b1000 A
b0 B
b1000 -n:7@
b0 >h<=Z
#9000000
b1001 A
b10000000 B
b1001 -n:7@
b10000000 >h<=Z
#10000000
b1010 A
b11000000 B
b1010 -n:7@
b11000000 >h<=Z
#11000000
b1011 A
b11100000 B
b1011 -n:7@
b11100000 >h<=Z
#12000000
b1100 A
b11110000 B
b1100 -n:7@
b11110000 >h<=Z
#13000000
b1101 A
b11111000 B
b1101 -n:7@
b11111000 >h<=Z
#14000000
b1110 A
b11111100 B
b1110 -n:7@
b11111100 >h<=Z
#15000000
b1111 A
b11111110 B
b1111 -n:7@
b11111110 >h<=Z
#16000000
b10000 A
b0 B
b10000 -n:7@
b0 >h<=Z
#17000000
b0 1
b0 A
1E
b0 F
b0 2zdj1
b0 -n:7@
1z,@WW
b0 B{KJS
#18000000
b11111111 1
b1 2
b11111111 B
b1 C
b1 D
b11111111 F
b1 G
b11111111 2zdj1
b1 =;m_[
b11111111 >h<=Z
b1 [xld3
b1 J+DYh
b11111111 B{KJS
b1 V'K*&
#19000000
b1111111 2
b100 3
b10 C
b100 D
b1111111 G
b100 H
b1111111 =;m_[
b100 @9Hd
b10 [xld3
b100 J+DYh
b1111111 V'K*&
b100 4zI$O
#20000000
b111111 3
b1001 4
b11 C
b1001 D
b111111 H
b1001 I
b111111 @9Hd
b1001 C:="|
b11 [xld3
b1001 J+DYh
b111111 4zI$O
b1001 %TTk[
#21000000
b11111 4
b10000 5
b100 C
b10000 D
b11111 I
b10000 J
b11111 C:="|
b10000 IDk7#
b100 [xld3
b10000 J+DYh
b11111 %TTk[
b10000 IgSeY
#22000000
b1111 5
b11001 6
b101 C
b11001 D
b1111 J
b11001 K
b1111 IDk7#
b11001 i]E1i
b101 [xld3
b11001 J+DYh
b1111 IgSeY
b11001 &&1T"
#23000000
b111 6
b100100 7
b110 C
b100100 D
b111 K
b100100 L
b111 i]E1i
b100100 tK,M]
b110 [xld3
b100100 J+DYh
b111 &&1T"
b100100 5)-l\
#24000000
b11 7
b110001 8
b111 C
b110001 D
b11 L
b110001 M
b11 tK,M]
b110001 tGp!\
b111 [xld3
b110001 J+DYh
b11 5)-l\
b110001 0RsLb
#25000000
b1 8
b1000000 9
b1000 C
b1000000 D
b1 M
b1000000 N
b1 tGp!\
b1000000 ."qjK
b1000 [xld3
b1000000 J+DYh
b1 0RsLb
b1000000 T>:}D
#26000000
b0 9
b1010001 :
b1001 C
b1010001 D
b0 N
b1010001 O
b0 ."qjK
b1010001 AUO:R
b1001 [xld3
b1010001 J+DYh
b0 T>:}D
b1010001 DPpZ*
#27000000
b10000000 :
b1100100 ;
b1010 C
b1100100 D
b10000000 O
b1100100 P
b10000000 AUO:R
b1100100 'kx`n
b1010 [xld3
b1100100 J+DYh
b10000000 DPpZ*
b1100100 %E(nf
#28000000
b11000000 ;
b1111001 <
b1011 C
b1111001 D
b11000000 P
b1111001 Q
b11000000 'kx`n
b1111001 U&(K\
b1011 [xld3
b1111001 J+DYh
b11000000 %E(nf
b1111001 2'pba
#29000000
b11100000 <
b10010000 =
b1100 C
b10010000 D
b11100000 Q
b10010000 R
b11100000 U&(K\
b10010000 q<O41
b1100 [xld3
b10010000 J+DYh
b11100000 2'pba
b10010000 e/c1:
#30000000
b11110000 =
b10101001 >
b1101 C
b10101001 D
b11110000 R
b10101001 S
b11110000 q<O41
b10101001 zvj)]
b1101 [xld3
b10101001 J+DYh
b11110000 e/c1:
b10101001 ;w.C7
#31000000
b11111000 >
b11000100 ?
b1110 C
b11000100 D
b11111000 S
b11000100 T
b11111000 zvj)]
b11000100 >0H<(
b1110 [xld3
b11000100 J+DYh
b11111000 ;w.C7
b11000100 fwdfu
#32000000
b11111100 ?
b11100001 @
b1111 C
b11100001 D
b11111100 T
b11100001 U
b11111100 >0H<(
b11100001 ARhXJ
b1111 [xld3
b11100001 J+DYh
b11111100 fwdfu
b11100001 *R\vx
#33000000
b11111110 @
b10000 C
b0 D
b11111110 U
b11111110 ARhXJ
b10000 [xld3
b0 J+DYh
b11111110 *R\vx
#34000000

View file

@ -1,14 +1,14 @@
$timescale 1 ps $end
$scope module conditional_assignment_last $end
$var wire 1 ! i $end
$var wire 1 " w $end
$var wire 1 xt~(W i $end
$var wire 1 6:7im w $end
$upscope $end
$enddefinitions $end
$dumpvars
0!
1"
0xt~(W
16:7im
$end
#1000000
1!
0"
1xt~(W
06:7im
#2000000

View file

@ -1,11 +1,11 @@
$timescale 1 ps $end
$scope module connect_const_reset $end
$var wire 1 ! reset_out $end
$var wire 1 " bit_out $end
$var wire 1 8ke|= reset_out $end
$var wire 1 {"c@= bit_out $end
$upscope $end
$enddefinitions $end
$dumpvars
1!
1"
18ke|=
1{"c@=
$end
#1000000

View file

@ -1,217 +1,217 @@
$timescale 1 ps $end
$scope module counter $end
$scope struct cd $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 1 `[J;" clk $end
$var wire 1 4pZx7 rst $end
$upscope $end
$var wire 4 # count $end
$var reg 4 $ count_reg $end
$var wire 4 rPs;{ count $end
$var reg 4 6_+(g count_reg $end
$upscope $end
$enddefinitions $end
$dumpvars
0!
0"
b0 #
b0 $
0`[J;"
04pZx7
b0 rPs;{
b0 6_+(g
$end
#500000
1"
b11 #
b11 $
14pZx7
b11 rPs;{
b11 6_+(g
#1000000
1!
1`[J;"
#1500000
0"
04pZx7
#2000000
0!
0`[J;"
#3000000
1!
b100 #
b100 $
1`[J;"
b100 rPs;{
b100 6_+(g
#4000000
0!
0`[J;"
#5000000
1!
b101 #
b101 $
1`[J;"
b101 rPs;{
b101 6_+(g
#6000000
0!
0`[J;"
#7000000
1!
b110 #
b110 $
1`[J;"
b110 rPs;{
b110 6_+(g
#8000000
0!
0`[J;"
#9000000
1!
b111 #
b111 $
1`[J;"
b111 rPs;{
b111 6_+(g
#10000000
0!
0`[J;"
#11000000
1!
b1000 #
b1000 $
1`[J;"
b1000 rPs;{
b1000 6_+(g
#12000000
0!
0`[J;"
#13000000
1!
b1001 #
b1001 $
1`[J;"
b1001 rPs;{
b1001 6_+(g
#14000000
0!
0`[J;"
#15000000
1!
b1010 #
b1010 $
1`[J;"
b1010 rPs;{
b1010 6_+(g
#16000000
0!
0`[J;"
#17000000
1!
b1011 #
b1011 $
1`[J;"
b1011 rPs;{
b1011 6_+(g
#18000000
0!
0`[J;"
#19000000
1!
b1100 #
b1100 $
1`[J;"
b1100 rPs;{
b1100 6_+(g
#20000000
0!
0`[J;"
#21000000
1!
b1101 #
b1101 $
1`[J;"
b1101 rPs;{
b1101 6_+(g
#22000000
0!
0`[J;"
#23000000
1!
b1110 #
b1110 $
1`[J;"
b1110 rPs;{
b1110 6_+(g
#24000000
0!
0`[J;"
#25000000
1!
b1111 #
b1111 $
1`[J;"
b1111 rPs;{
b1111 6_+(g
#26000000
0!
0`[J;"
#27000000
1!
b0 #
b0 $
1`[J;"
b0 rPs;{
b0 6_+(g
#28000000
0!
0`[J;"
#29000000
1!
b1 #
b1 $
1`[J;"
b1 rPs;{
b1 6_+(g
#30000000
0!
0`[J;"
#31000000
1!
b10 #
b10 $
1`[J;"
b10 rPs;{
b10 6_+(g
#32000000
0!
0`[J;"
#33000000
1!
b11 #
b11 $
1`[J;"
b11 rPs;{
b11 6_+(g
#34000000
0!
0`[J;"
#35000000
1!
b100 #
b100 $
1`[J;"
b100 rPs;{
b100 6_+(g
#36000000
0!
0`[J;"
#37000000
1!
b101 #
b101 $
1`[J;"
b101 rPs;{
b101 6_+(g
#38000000
0!
0`[J;"
#39000000
1!
b110 #
b110 $
1`[J;"
b110 rPs;{
b110 6_+(g
#40000000
0!
0`[J;"
#41000000
1!
b111 #
b111 $
1`[J;"
b111 rPs;{
b111 6_+(g
#42000000
0!
0`[J;"
#43000000
1!
b1000 #
b1000 $
1`[J;"
b1000 rPs;{
b1000 6_+(g
#44000000
0!
0`[J;"
#45000000
1!
b1001 #
b1001 $
1`[J;"
b1001 rPs;{
b1001 6_+(g
#46000000
0!
0`[J;"
#47000000
1!
b1010 #
b1010 $
1`[J;"
b1010 rPs;{
b1010 6_+(g
#48000000
0!
0`[J;"
#49000000
1!
b1011 #
b1011 $
1`[J;"
b1011 rPs;{
b1011 6_+(g
#50000000
0!
0`[J;"
#51000000
1!
b1100 #
b1100 $
1`[J;"
b1100 rPs;{
b1100 6_+(g
#52000000
0!
0`[J;"
#53000000
1!
b1101 #
b1101 $
1`[J;"
b1101 rPs;{
b1101 6_+(g
#54000000
0!
0`[J;"
#55000000
1!
b1110 #
b1110 $
1`[J;"
b1110 rPs;{
b1110 6_+(g
#56000000
0!
0`[J;"
#57000000
1!
b1111 #
b1111 $
1`[J;"
b1111 rPs;{
b1111 6_+(g
#58000000
0!
0`[J;"
#59000000
1!
b0 #
b0 $
1`[J;"
b0 rPs;{
b0 6_+(g
#60000000
0!
0`[J;"
#61000000
1!
b1 #
b1 $
1`[J;"
b1 rPs;{
b1 6_+(g
#62000000
0!
0`[J;"
#63000000
1!
b10 #
b10 $
1`[J;"
b10 rPs;{
b10 6_+(g
#64000000
0!
0`[J;"
#65000000
1!
b11 #
b11 $
1`[J;"
b11 rPs;{
b11 6_+(g
#66000000

View file

@ -1,214 +1,214 @@
$timescale 1 ps $end
$scope module counter $end
$scope struct cd $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 1 `[J;" clk $end
$var wire 1 4pZx7 rst $end
$upscope $end
$var wire 4 # count $end
$var reg 4 $ count_reg $end
$var wire 4 rPs;{ count $end
$var reg 4 6_+(g count_reg $end
$upscope $end
$enddefinitions $end
$dumpvars
0!
1"
b0 #
b0 $
0`[J;"
14pZx7
b0 rPs;{
b0 6_+(g
$end
#1000000
1!
b11 #
b11 $
0"
1`[J;"
b11 rPs;{
b11 6_+(g
04pZx7
#2000000
0!
0`[J;"
#3000000
1!
b100 #
b100 $
1`[J;"
b100 rPs;{
b100 6_+(g
#4000000
0!
0`[J;"
#5000000
1!
b101 #
b101 $
1`[J;"
b101 rPs;{
b101 6_+(g
#6000000
0!
0`[J;"
#7000000
1!
b110 #
b110 $
1`[J;"
b110 rPs;{
b110 6_+(g
#8000000
0!
0`[J;"
#9000000
1!
b111 #
b111 $
1`[J;"
b111 rPs;{
b111 6_+(g
#10000000
0!
0`[J;"
#11000000
1!
b1000 #
b1000 $
1`[J;"
b1000 rPs;{
b1000 6_+(g
#12000000
0!
0`[J;"
#13000000
1!
b1001 #
b1001 $
1`[J;"
b1001 rPs;{
b1001 6_+(g
#14000000
0!
0`[J;"
#15000000
1!
b1010 #
b1010 $
1`[J;"
b1010 rPs;{
b1010 6_+(g
#16000000
0!
0`[J;"
#17000000
1!
b1011 #
b1011 $
1`[J;"
b1011 rPs;{
b1011 6_+(g
#18000000
0!
0`[J;"
#19000000
1!
b1100 #
b1100 $
1`[J;"
b1100 rPs;{
b1100 6_+(g
#20000000
0!
0`[J;"
#21000000
1!
b1101 #
b1101 $
1`[J;"
b1101 rPs;{
b1101 6_+(g
#22000000
0!
0`[J;"
#23000000
1!
b1110 #
b1110 $
1`[J;"
b1110 rPs;{
b1110 6_+(g
#24000000
0!
0`[J;"
#25000000
1!
b1111 #
b1111 $
1`[J;"
b1111 rPs;{
b1111 6_+(g
#26000000
0!
0`[J;"
#27000000
1!
b0 #
b0 $
1`[J;"
b0 rPs;{
b0 6_+(g
#28000000
0!
0`[J;"
#29000000
1!
b1 #
b1 $
1`[J;"
b1 rPs;{
b1 6_+(g
#30000000
0!
0`[J;"
#31000000
1!
b10 #
b10 $
1`[J;"
b10 rPs;{
b10 6_+(g
#32000000
0!
0`[J;"
#33000000
1!
b11 #
b11 $
1`[J;"
b11 rPs;{
b11 6_+(g
#34000000
0!
0`[J;"
#35000000
1!
b100 #
b100 $
1`[J;"
b100 rPs;{
b100 6_+(g
#36000000
0!
0`[J;"
#37000000
1!
b101 #
b101 $
1`[J;"
b101 rPs;{
b101 6_+(g
#38000000
0!
0`[J;"
#39000000
1!
b110 #
b110 $
1`[J;"
b110 rPs;{
b110 6_+(g
#40000000
0!
0`[J;"
#41000000
1!
b111 #
b111 $
1`[J;"
b111 rPs;{
b111 6_+(g
#42000000
0!
0`[J;"
#43000000
1!
b1000 #
b1000 $
1`[J;"
b1000 rPs;{
b1000 6_+(g
#44000000
0!
0`[J;"
#45000000
1!
b1001 #
b1001 $
1`[J;"
b1001 rPs;{
b1001 6_+(g
#46000000
0!
0`[J;"
#47000000
1!
b1010 #
b1010 $
1`[J;"
b1010 rPs;{
b1010 6_+(g
#48000000
0!
0`[J;"
#49000000
1!
b1011 #
b1011 $
1`[J;"
b1011 rPs;{
b1011 6_+(g
#50000000
0!
0`[J;"
#51000000
1!
b1100 #
b1100 $
1`[J;"
b1100 rPs;{
b1100 6_+(g
#52000000
0!
0`[J;"
#53000000
1!
b1101 #
b1101 $
1`[J;"
b1101 rPs;{
b1101 6_+(g
#54000000
0!
0`[J;"
#55000000
1!
b1110 #
b1110 $
1`[J;"
b1110 rPs;{
b1110 6_+(g
#56000000
0!
0`[J;"
#57000000
1!
b1111 #
b1111 $
1`[J;"
b1111 rPs;{
b1111 6_+(g
#58000000
0!
0`[J;"
#59000000
1!
b0 #
b0 $
1`[J;"
b0 rPs;{
b0 6_+(g
#60000000
0!
0`[J;"
#61000000
1!
b1 #
b1 $
1`[J;"
b1 rPs;{
b1 6_+(g
#62000000
0!
0`[J;"
#63000000
1!
b10 #
b10 $
1`[J;"
b10 rPs;{
b10 6_+(g
#64000000
0!
0`[J;"
#65000000
1!
b11 #
b11 $
1`[J;"
b11 rPs;{
b11 6_+(g
#66000000

View file

@ -1,11 +1,11 @@
$timescale 1 ps $end
$scope module duplicate_names $end
$var wire 8 ! w $end
$var wire 8 " w_2 $end
$var wire 8 7[_7. w $end
$var wire 8 7[_7." w_2 $end
$upscope $end
$enddefinitions $end
$dumpvars
b101 !
b110 "
b101 7[_7.
b110 7[_7."
$end
#1000000

View file

@ -1,126 +1,126 @@
$timescale 1 ps $end
$scope module enums $end
$scope struct cd $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 1 0n\U< clk $end
$var wire 1 a?A!) rst $end
$upscope $end
$var wire 1 # en $end
$var wire 2 $ which_in $end
$var wire 4 % data_in $end
$var wire 2 & which_out $end
$var wire 4 ' data_out $end
$var wire 1 #ZQY# en $end
$var wire 2 8?II+ which_in $end
$var wire 4 OO,N+ data_in $end
$var wire 2 yr2gr which_out $end
$var wire 4 q_O;Y data_out $end
$scope struct b_out $end
$var string 1 ( \$tag $end
$var string 1 7L1gf \$tag $end
$scope struct HdlSome $end
$var wire 1 ) \0 $end
$var wire 1 * \1 $end
$var wire 1 EO?Ju \0 $end
$var wire 1 cGtNN \1 $end
$upscope $end
$upscope $end
$scope struct b2_out $end
$var string 1 + \$tag $end
$var string 1 dqd@B \$tag $end
$scope struct HdlSome $end
$var wire 1 , \0 $end
$var wire 1 - \1 $end
$var wire 1 (FG:I \0 $end
$var wire 1 dzy-= \1 $end
$upscope $end
$upscope $end
$scope struct the_reg $end
$var string 1 . \$tag $end
$var string 1 J#9uO \$tag $end
$scope struct B $end
$var reg 1 / \0 $end
$var reg 1 0 \1 $end
$var reg 1 ca2Gh \0 $end
$var reg 1 f)r)? \1 $end
$upscope $end
$scope struct C $end
$scope struct a $end
$var reg 1 1 \[0] $end
$var reg 1 2 \[1] $end
$var reg 1 ;BepJ \[0] $end
$var reg 1 J~2;e \[1] $end
$upscope $end
$var reg 2 3 b $end
$var reg 2 w\b)K b $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
0!
1"
0#
b0 $
b0 %
b0 &
b0 '
sHdlNone\x20(0) (
0)
0*
sHdlNone\x20(0) +
0,
0-
sA\x20(0) .
0/
00
01
02
b0 3
00n\U<
1a?A!)
0#ZQY#
b0 8?II+
b0 OO,N+
b0 yr2gr
b0 q_O;Y
sHdlNone\x20(0) 7L1gf
0EO?Ju
0cGtNN
sHdlNone\x20(0) dqd@B
0(FG:I
0dzy-=
sA\x20(0) J#9uO
0ca2Gh
0f)r)?
0;BepJ
0J~2;e
b0 w\b)K
$end
#1000000
1!
10n\U<
#1100000
0"
0a?A!)
#2000000
0!
00n\U<
#3000000
1!
10n\U<
#4000000
1#
b1 $
0!
1#ZQY#
b1 8?II+
00n\U<
#5000000
1!
b1 &
sHdlSome\x20(1) (
sHdlSome\x20(1) +
sB\x20(1) .
10n\U<
b1 yr2gr
sHdlSome\x20(1) 7L1gf
sHdlSome\x20(1) dqd@B
sB\x20(1) J#9uO
#6000000
0#
b0 $
0!
0#ZQY#
b0 8?II+
00n\U<
#7000000
1!
10n\U<
#8000000
1#
b1 $
b1111 %
0!
1#ZQY#
b1 8?II+
b1111 OO,N+
00n\U<
#9000000
1!
b11 '
1)
1*
1,
1-
1/
10
11
12
10n\U<
b11 q_O;Y
1EO?Ju
1cGtNN
1(FG:I
1dzy-=
1ca2Gh
1f)r)?
1;BepJ
1J~2;e
#10000000
0!
00n\U<
#11000000
1!
10n\U<
#12000000
b10 $
0!
b10 8?II+
00n\U<
#13000000
1!
b10 &
b1111 '
sHdlNone\x20(0) (
0)
0*
sHdlNone\x20(0) +
0,
0-
sC\x20(2) .
b11 3
10n\U<
b10 yr2gr
b1111 q_O;Y
sHdlNone\x20(0) 7L1gf
0EO?Ju
0cGtNN
sHdlNone\x20(0) dqd@B
0(FG:I
0dzy-=
sC\x20(2) J#9uO
b11 w\b)K
#14000000
0!
00n\U<
#15000000
1!
10n\U<
#16000000

View file

@ -1,52 +1,52 @@
$timescale 1 ps $end
$scope module extern_module $end
$var wire 1 ! i $end
$var wire 1 " o $end
$var wire 1 `MLd_ i $end
$var wire 1 ^;OnJ o $end
$upscope $end
$enddefinitions $end
$dumpvars
0!
0"
0`MLd_
0^;OnJ
$end
1"
1^;OnJ
#500000
#1500000
0"
0^;OnJ
#2500000
1"
1^;OnJ
#3500000
0"
0^;OnJ
#4500000
1"
1^;OnJ
#5500000
0"
0^;OnJ
#6500000
1"
1^;OnJ
#7500000
0"
0^;OnJ
#8500000
1"
1^;OnJ
#9500000
0"
0^;OnJ
#10000000
1!
1`MLd_
#10500000
#11500000
1"
1^;OnJ
#12500000
0"
0^;OnJ
#13500000
1"
1^;OnJ
#14500000
0"
0^;OnJ
#15500000
1"
1^;OnJ
#16500000
0"
0^;OnJ
#17500000
1"
1^;OnJ
#18500000
0"
0^;OnJ
#19500000
1"
1^;OnJ
#20000000

View file

@ -1,151 +1,151 @@
$timescale 1 ps $end
$scope module extern_module2 $end
$var wire 1 ! en $end
$var wire 1 " clk $end
$var wire 8 # o $end
$var wire 1 oHT(x en $end
$var wire 1 nHT-: clk $end
$var wire 8 0:wF& o $end
$upscope $end
$enddefinitions $end
$dumpvars
1!
0"
b0 #
1oHT(x
0nHT-:
b0 0:wF&
$end
b1001000 #
b1001000 0:wF&
#1000000
1"
b1100101 #
1nHT-:
b1100101 0:wF&
#2000000
0"
0nHT-:
#3000000
1"
b1101100 #
1nHT-:
b1101100 0:wF&
#4000000
0"
0nHT-:
#5000000
1"
1nHT-:
#6000000
0"
0nHT-:
#7000000
1"
b1101111 #
1nHT-:
b1101111 0:wF&
#8000000
0"
0nHT-:
#9000000
1"
b101100 #
1nHT-:
b101100 0:wF&
#10000000
0!
0"
0oHT(x
0nHT-:
#11000000
1"
1nHT-:
#12000000
0"
0nHT-:
#13000000
1"
1nHT-:
#14000000
0"
0nHT-:
#15000000
1"
1nHT-:
#16000000
0"
0nHT-:
#17000000
1"
1nHT-:
#18000000
0"
0nHT-:
#19000000
1"
1nHT-:
#20000000
1!
0"
1oHT(x
0nHT-:
#21000000
1"
b100000 #
1nHT-:
b100000 0:wF&
#22000000
0"
0nHT-:
#23000000
1"
b1010111 #
1nHT-:
b1010111 0:wF&
#24000000
0"
0nHT-:
#25000000
1"
b1101111 #
1nHT-:
b1101111 0:wF&
#26000000
0"
0nHT-:
#27000000
1"
b1110010 #
1nHT-:
b1110010 0:wF&
#28000000
0"
0nHT-:
#29000000
1"
b1101100 #
1nHT-:
b1101100 0:wF&
#30000000
0!
0"
0oHT(x
0nHT-:
#31000000
1"
1nHT-:
#32000000
0"
0nHT-:
#33000000
1"
1nHT-:
#34000000
0"
0nHT-:
#35000000
1"
1nHT-:
#36000000
0"
0nHT-:
#37000000
1"
1nHT-:
#38000000
0"
0nHT-:
#39000000
1"
1nHT-:
#40000000
1!
0"
1oHT(x
0nHT-:
#41000000
1"
b1100100 #
1nHT-:
b1100100 0:wF&
#42000000
0"
0nHT-:
#43000000
1"
b100001 #
1nHT-:
b100001 0:wF&
#44000000
0"
0nHT-:
#45000000
1"
b1010 #
1nHT-:
b1010 0:wF&
#46000000
0"
0nHT-:
#47000000
1"
b1001000 #
1nHT-:
b1001000 0:wF&
#48000000
0"
0nHT-:
#49000000
1"
b1100101 #
1nHT-:
b1100101 0:wF&
#50000000
0!
0"
0oHT(x
0nHT-:
#51000000
1"
1nHT-:
#52000000
0"
0nHT-:
#53000000
1"
1nHT-:
#54000000
0"
0nHT-:
#55000000
1"
1nHT-:
#56000000
0"
0nHT-:
#57000000
1"
1nHT-:
#58000000
0"
0nHT-:
#59000000
1"
1nHT-:
#60000000

File diff suppressed because it is too large Load diff

View file

@ -1,408 +1,408 @@
$timescale 1 ps $end
$scope module memories $end
$scope struct r $end
$var wire 4 ! addr $end
$var wire 1 " en $end
$var wire 1 # clk $end
$var wire 4 z&0Qk addr $end
$var wire 1 o.T)# en $end
$var wire 1 :XNoK clk $end
$scope struct data $end
$var wire 8 $ \0 $end
$var wire 8 % \1 $end
$var wire 8 Cq]A% \0 $end
$var wire 8 avKNj \1 $end
$upscope $end
$upscope $end
$scope struct w $end
$var wire 4 & addr $end
$var wire 1 ' en $end
$var wire 1 ( clk $end
$var wire 4 p<O.M addr $end
$var wire 1 #9)l8 en $end
$var wire 1 QX!^| clk $end
$scope struct data $end
$var wire 8 ) \0 $end
$var wire 8 * \1 $end
$var wire 8 G"IXQ \0 $end
$var wire 8 h\t:E \1 $end
$upscope $end
$scope struct mask $end
$var wire 1 + \0 $end
$var wire 1 , \1 $end
$var wire 1 FCuNz \0 $end
$var wire 1 /Y7%J \1 $end
$upscope $end
$upscope $end
$scope struct mem $end
$scope struct contents $end
$scope struct \[0] $end
$scope struct mem $end
$var reg 8 9 \0 $end
$var reg 8 I \1 $end
$var reg 8 4d[cL \0 $end
$var reg 8 {qEUV \1 $end
$upscope $end
$upscope $end
$scope struct \[1] $end
$scope struct mem $end
$var reg 8 : \0 $end
$var reg 8 J \1 $end
$var reg 8 c`NPR \0 $end
$var reg 8 vK:33 \1 $end
$upscope $end
$upscope $end
$scope struct \[2] $end
$scope struct mem $end
$var reg 8 ; \0 $end
$var reg 8 K \1 $end
$var reg 8 ihYp_ \0 $end
$var reg 8 QZb%P \1 $end
$upscope $end
$upscope $end
$scope struct \[3] $end
$scope struct mem $end
$var reg 8 < \0 $end
$var reg 8 L \1 $end
$var reg 8 ,O%<$ \0 $end
$var reg 8 @?uSf \1 $end
$upscope $end
$upscope $end
$scope struct \[4] $end
$scope struct mem $end
$var reg 8 = \0 $end
$var reg 8 M \1 $end
$var reg 8 N[IF& \0 $end
$var reg 8 Zf9lw \1 $end
$upscope $end
$upscope $end
$scope struct \[5] $end
$scope struct mem $end
$var reg 8 > \0 $end
$var reg 8 N \1 $end
$var reg 8 dr6lq \0 $end
$var reg 8 fc"UR \1 $end
$upscope $end
$upscope $end
$scope struct \[6] $end
$scope struct mem $end
$var reg 8 ? \0 $end
$var reg 8 O \1 $end
$var reg 8 xpw5\ \0 $end
$var reg 8 dd$?K \1 $end
$upscope $end
$upscope $end
$scope struct \[7] $end
$scope struct mem $end
$var reg 8 @ \0 $end
$var reg 8 P \1 $end
$var reg 8 vH;}2 \0 $end
$var reg 8 ILB?4 \1 $end
$upscope $end
$upscope $end
$scope struct \[8] $end
$scope struct mem $end
$var reg 8 A \0 $end
$var reg 8 Q \1 $end
$var reg 8 /X4v> \0 $end
$var reg 8 &V*EE \1 $end
$upscope $end
$upscope $end
$scope struct \[9] $end
$scope struct mem $end
$var reg 8 B \0 $end
$var reg 8 R \1 $end
$var reg 8 IczZe \0 $end
$var reg 8 unX>R \1 $end
$upscope $end
$upscope $end
$scope struct \[10] $end
$scope struct mem $end
$var reg 8 C \0 $end
$var reg 8 S \1 $end
$var reg 8 0hTyY \0 $end
$var reg 8 9K_w) \1 $end
$upscope $end
$upscope $end
$scope struct \[11] $end
$scope struct mem $end
$var reg 8 D \0 $end
$var reg 8 T \1 $end
$var reg 8 +C/Sz \0 $end
$var reg 8 }Y{:o \1 $end
$upscope $end
$upscope $end
$scope struct \[12] $end
$scope struct mem $end
$var reg 8 E \0 $end
$var reg 8 U \1 $end
$var reg 8 S6-5u \0 $end
$var reg 8 9q6)w \1 $end
$upscope $end
$upscope $end
$scope struct \[13] $end
$scope struct mem $end
$var reg 8 F \0 $end
$var reg 8 V \1 $end
$var reg 8 !c<w* \0 $end
$var reg 8 Ve@)M \1 $end
$upscope $end
$upscope $end
$scope struct \[14] $end
$scope struct mem $end
$var reg 8 G \0 $end
$var reg 8 W \1 $end
$var reg 8 OiF9* \0 $end
$var reg 8 Ylyz~ \1 $end
$upscope $end
$upscope $end
$scope struct \[15] $end
$scope struct mem $end
$var reg 8 H \0 $end
$var reg 8 X \1 $end
$var reg 8 ?+m9D \0 $end
$var reg 8 A6sb~ \1 $end
$upscope $end
$upscope $end
$upscope $end
$scope struct r0 $end
$var wire 4 - addr $end
$var wire 1 . en $end
$var wire 1 / clk $end
$var wire 4 ="2wN addr $end
$var wire 1 jy78F en $end
$var wire 1 \o>8T clk $end
$scope struct data $end
$var wire 8 0 \0 $end
$var wire 8 1 \1 $end
$var wire 8 \k#l \0 $end
$var wire 8 olx7O \1 $end
$upscope $end
$upscope $end
$scope struct w1 $end
$var wire 4 2 addr $end
$var wire 1 3 en $end
$var wire 1 4 clk $end
$var wire 4 H,W!J addr $end
$var wire 1 "7?3I en $end
$var wire 1 DC/;" clk $end
$scope struct data $end
$var wire 8 5 \0 $end
$var wire 8 6 \1 $end
$var wire 8 0DrV' \0 $end
$var wire 8 wa!Cx \1 $end
$upscope $end
$scope struct mask $end
$var wire 1 7 \0 $end
$var wire 1 8 \1 $end
$var wire 1 u^b&R \0 $end
$var wire 1 Ic\|v \1 $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
b1 9
b100011 I
b1 :
b100011 J
b1 ;
b100011 K
b1 <
b100011 L
b1 =
b100011 M
b1 >
b100011 N
b1 ?
b100011 O
b1 @
b100011 P
b1 A
b100011 Q
b1 B
b100011 R
b1 C
b100011 S
b1 D
b100011 T
b1 E
b100011 U
b1 F
b100011 V
b1 G
b100011 W
b1 H
b100011 X
b0 !
0"
0#
b0 $
b0 %
b0 &
0'
0(
b0 )
b0 *
0+
0,
b0 -
0.
0/
b0 0
b0 1
b0 2
03
04
b0 5
b0 6
07
08
b1 4d[cL
b100011 {qEUV
b1 c`NPR
b100011 vK:33
b1 ihYp_
b100011 QZb%P
b1 ,O%<$
b100011 @?uSf
b1 N[IF&
b100011 Zf9lw
b1 dr6lq
b100011 fc"UR
b1 xpw5\
b100011 dd$?K
b1 vH;}2
b100011 ILB?4
b1 /X4v>
b100011 &V*EE
b1 IczZe
b100011 unX>R
b1 0hTyY
b100011 9K_w)
b1 +C/Sz
b100011 }Y{:o
b1 S6-5u
b100011 9q6)w
b1 !c<w*
b100011 Ve@)M
b1 OiF9*
b100011 Ylyz~
b1 ?+m9D
b100011 A6sb~
b0 z&0Qk
0o.T)#
0:XNoK
b0 Cq]A%
b0 avKNj
b0 p<O.M
0#9)l8
0QX!^|
b0 G"IXQ
b0 h\t:E
0FCuNz
0/Y7%J
b0 ="2wN
0jy78F
0\o>8T
b0 \k#l
b0 olx7O
b0 H,W!J
0"7?3I
0DC/;"
b0 0DrV'
b0 wa!Cx
0u^b&R
0Ic\|v
$end
#1000000
1#
1(
1/
14
1:XNoK
1QX!^|
1\o>8T
1DC/;"
#2000000
1"
0#
b1 $
b100011 %
1'
0(
b10000 )
b100000 *
1+
1,
1.
0/
b1 0
b100011 1
13
04
b10000 5
b100000 6
17
18
1o.T)#
0:XNoK
b1 Cq]A%
b100011 avKNj
1#9)l8
0QX!^|
b10000 G"IXQ
b100000 h\t:E
1FCuNz
1/Y7%J
1jy78F
0\o>8T
b1 \k#l
b100011 olx7O
1"7?3I
0DC/;"
b10000 0DrV'
b100000 wa!Cx
1u^b&R
1Ic\|v
#3000000
b10000 9
b100000 I
1#
b10000 $
b100000 %
1(
1/
b10000 0
b100000 1
14
b10000 4d[cL
b100000 {qEUV
1:XNoK
b10000 Cq]A%
b100000 avKNj
1QX!^|
1\o>8T
b10000 \k#l
b100000 olx7O
1DC/;"
#4000000
0#
0(
b110000 )
b1000000 *
0+
0/
04
b110000 5
b1000000 6
07
0:XNoK
0QX!^|
b110000 G"IXQ
b1000000 h\t:E
0FCuNz
0\o>8T
0DC/;"
b110000 0DrV'
b1000000 wa!Cx
0u^b&R
#5000000
b10000 9
b1000000 I
1#
b1000000 %
1(
1/
b1000000 1
14
b10000 4d[cL
b1000000 {qEUV
1:XNoK
b1000000 avKNj
1QX!^|
1\o>8T
b1000000 olx7O
1DC/;"
#6000000
0#
0(
b1010000 )
b1100000 *
1+
0,
0/
04
b1010000 5
b1100000 6
17
08
0:XNoK
0QX!^|
b1010000 G"IXQ
b1100000 h\t:E
1FCuNz
0/Y7%J
0\o>8T
0DC/;"
b1010000 0DrV'
b1100000 wa!Cx
1u^b&R
0Ic\|v
#7000000
b1010000 9
b1000000 I
1#
b1010000 $
1(
1/
b1010000 0
14
b1010000 4d[cL
b1000000 {qEUV
1:XNoK
b1010000 Cq]A%
1QX!^|
1\o>8T
b1010000 \k#l
1DC/;"
#8000000
0#
0(
b1110000 )
b10000000 *
0+
0/
04
b1110000 5
b10000000 6
07
0:XNoK
0QX!^|
b1110000 G"IXQ
b10000000 h\t:E
0FCuNz
0\o>8T
0DC/;"
b1110000 0DrV'
b10000000 wa!Cx
0u^b&R
#9000000
1#
1(
1/
14
1:XNoK
1QX!^|
1\o>8T
1DC/;"
#10000000
0#
0'
0(
b10010000 )
b10100000 *
0/
03
04
b10010000 5
b10100000 6
0:XNoK
0#9)l8
0QX!^|
b10010000 G"IXQ
b10100000 h\t:E
0\o>8T
0"7?3I
0DC/;"
b10010000 0DrV'
b10100000 wa!Cx
#11000000
1#
1(
1/
14
1:XNoK
1QX!^|
1\o>8T
1DC/;"
#12000000
0#
b1 &
1'
0(
1+
1,
0/
b1 2
13
04
17
18
0:XNoK
b1 p<O.M
1#9)l8
0QX!^|
1FCuNz
1/Y7%J
0\o>8T
b1 H,W!J
1"7?3I
0DC/;"
1u^b&R
1Ic\|v
#13000000
b10010000 :
b10100000 J
1#
1(
1/
14
b10010000 c`NPR
b10100000 vK:33
1:XNoK
1QX!^|
1\o>8T
1DC/;"
#14000000
0#
b10 &
0(
b10110000 )
b11000000 *
0/
b10 2
04
b10110000 5
b11000000 6
0:XNoK
b10 p<O.M
0QX!^|
b10110000 G"IXQ
b11000000 h\t:E
0\o>8T
b10 H,W!J
0DC/;"
b10110000 0DrV'
b11000000 wa!Cx
#15000000
b10110000 ;
b11000000 K
1#
1(
1/
14
b10110000 ihYp_
b11000000 QZb%P
1:XNoK
1QX!^|
1\o>8T
1DC/;"
#16000000
0#
0'
0(
b11010000 )
b11100000 *
0/
03
04
b11010000 5
b11100000 6
0:XNoK
0#9)l8
0QX!^|
b11010000 G"IXQ
b11100000 h\t:E
0\o>8T
0"7?3I
0DC/;"
b11010000 0DrV'
b11100000 wa!Cx
#17000000
1#
1(
1/
14
1:XNoK
1QX!^|
1\o>8T
1DC/;"
#18000000
b1 !
0#
b10010000 $
b10100000 %
0(
b1 -
0/
b10010000 0
b10100000 1
04
b1 z&0Qk
0:XNoK
b10010000 Cq]A%
b10100000 avKNj
0QX!^|
b1 ="2wN
0\o>8T
b10010000 \k#l
b10100000 olx7O
0DC/;"
#19000000
1#
1(
1/
14
1:XNoK
1QX!^|
1\o>8T
1DC/;"
#20000000
b10 !
0#
b10110000 $
b11000000 %
0(
b10 -
0/
b10110000 0
b11000000 1
04
b10 z&0Qk
0:XNoK
b10110000 Cq]A%
b11000000 avKNj
0QX!^|
b10 ="2wN
0\o>8T
b10110000 \k#l
b11000000 olx7O
0DC/;"
#21000000
1#
1(
1/
14
1:XNoK
1QX!^|
1\o>8T
1DC/;"
#22000000
0#
0(
0/
04
0:XNoK
0QX!^|
0\o>8T
0DC/;"

View file

@ -1,363 +1,363 @@
$timescale 1 ps $end
$scope module memories2 $end
$scope struct rw $end
$var wire 3 ! addr $end
$var wire 1 " en $end
$var wire 1 # clk $end
$var wire 2 $ rdata $end
$var wire 1 % wmode $end
$var wire 2 & wdata $end
$var wire 1 ' wmask $end
$var wire 3 xkkG> addr $end
$var wire 1 HoA{1 en $end
$var wire 1 C*2BQ clk $end
$var wire 2 ueF!x rdata $end
$var wire 1 m\l/p wmode $end
$var wire 2 WmjEh wdata $end
$var wire 1 +3E@H wmask $end
$upscope $end
$scope struct mem $end
$scope struct contents $end
$scope struct \[0] $end
$scope struct mem $end
$var string 1 1 \$tag $end
$var reg 1 6 HdlSome $end
$var string 1 ujd9u \$tag $end
$var reg 1 *5lV# HdlSome $end
$upscope $end
$upscope $end
$scope struct \[1] $end
$scope struct mem $end
$var string 1 2 \$tag $end
$var reg 1 7 HdlSome $end
$var string 1 *qL|n \$tag $end
$var reg 1 ^/FDC HdlSome $end
$upscope $end
$upscope $end
$scope struct \[2] $end
$scope struct mem $end
$var string 1 3 \$tag $end
$var reg 1 8 HdlSome $end
$var string 1 r*7|@ \$tag $end
$var reg 1 YMY"3 HdlSome $end
$upscope $end
$upscope $end
$scope struct \[3] $end
$scope struct mem $end
$var string 1 4 \$tag $end
$var reg 1 9 HdlSome $end
$var string 1 jj/6F \$tag $end
$var reg 1 S+Uy} HdlSome $end
$upscope $end
$upscope $end
$scope struct \[4] $end
$scope struct mem $end
$var string 1 5 \$tag $end
$var reg 1 : HdlSome $end
$var string 1 H72IP \$tag $end
$var reg 1 vH{({ HdlSome $end
$upscope $end
$upscope $end
$upscope $end
$scope struct rw0 $end
$var wire 3 ( addr $end
$var wire 1 ) en $end
$var wire 1 * clk $end
$var wire 3 uabMI addr $end
$var wire 1 LEn[l en $end
$var wire 1 OpH)U clk $end
$scope struct rdata $end
$var string 1 + \$tag $end
$var wire 1 , HdlSome $end
$var string 1 [}rcZ \$tag $end
$var wire 1 5f=Y~ HdlSome $end
$upscope $end
$var wire 1 - wmode $end
$var wire 1 6c_9_ wmode $end
$scope struct wdata $end
$var string 1 . \$tag $end
$var wire 1 / HdlSome $end
$var string 1 $hfRN \$tag $end
$var wire 1 rop,b HdlSome $end
$upscope $end
$var wire 1 0 wmask $end
$var wire 1 Ly=US wmask $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
sHdlSome\x20(1) 1
16
sHdlSome\x20(1) 2
17
sHdlSome\x20(1) 3
18
sHdlSome\x20(1) 4
19
sHdlSome\x20(1) 5
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05f=Y~
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sHdlNone\x20(0) $hfRN
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0Ly=US
$end
#250000
1#
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#750000
0#
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sHdlNone\x20(0) 1
06
1#
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sHdlNone\x20(0) ujd9u
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1%
b11 &
1-
sHdlSome\x20(1) .
1/
1m\l/p
b11 WmjEh
16c_9_
sHdlSome\x20(1) $hfRN
1rop,b
#5250000
1#
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#5500000
#5750000
0#
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#6000000
b1 !
b1 &
1'
b1 (
0/
10
b1 xkkG>
b1 WmjEh
1+3E@H
b1 uabMI
0rop,b
1Ly=US
#6250000
sHdlSome\x20(1) 2
07
1#
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0^/FDC
1C*2BQ
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#6500000
#6750000
0#
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0C*2BQ
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#7000000
b10 !
b10 &
b10 (
sHdlNone\x20(0) .
b10 xkkG>
b10 WmjEh
b10 uabMI
sHdlNone\x20(0) $hfRN
#7250000
sHdlNone\x20(0) 3
08
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0YMY"3
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#7500000
#7750000
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#8000000
b11 !
b11 &
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sHdlSome\x20(1) .
1/
b11 xkkG>
b11 WmjEh
b11 uabMI
sHdlSome\x20(1) $hfRN
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#8250000
sHdlSome\x20(1) 4
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1#
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sHdlSome\x20(1) jj/6F
1S+Uy}
1C*2BQ
1OpH)U
#8500000
#8750000
0#
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0OpH)U
#9000000
b100 !
b10 &
b100 (
sHdlNone\x20(0) .
0/
b100 xkkG>
b10 WmjEh
b100 uabMI
sHdlNone\x20(0) $hfRN
0rop,b
#9250000
sHdlNone\x20(0) 5
0:
1#
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sHdlNone\x20(0) H72IP
0vH{({
1C*2BQ
1OpH)U
#9500000
#9750000
0#
0*
0C*2BQ
0OpH)U
#10000000
b101 !
b1 &
b101 (
sHdlSome\x20(1) .
b101 xkkG>
b1 WmjEh
b101 uabMI
sHdlSome\x20(1) $hfRN
#10250000
1#
1*
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#10500000
#10750000
0#
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0C*2BQ
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#11000000
b110 !
b110 (
b110 xkkG>
b110 uabMI
#11250000
1#
1*
1C*2BQ
1OpH)U
#11500000
#11750000
0#
0*
0C*2BQ
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#12000000
b111 !
b111 (
b111 xkkG>
b111 uabMI
#12250000
1#
1*
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#12500000
#12750000
0#
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#13000000
0%
b0 &
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sHdlNone\x20(0) .
00
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b0 WmjEh
0+3E@H
06c_9_
sHdlNone\x20(0) $hfRN
0Ly=US
#13250000
1#
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#13500000
#13750000
0#
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#14000000
b110 !
b110 (
b110 xkkG>
b110 uabMI
#14250000
1#
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#14500000
#14750000
0#
0*
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#15000000
b101 !
b101 (
b101 xkkG>
b101 uabMI
#15250000
1#
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#15750000
0#
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b100 !
b100 (
b100 xkkG>
b100 uabMI
#16250000
1#
1*
1C*2BQ
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#16500000
#16750000
0#
0*
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#17000000
b11 !
b11 (
b11 xkkG>
b11 uabMI
#17250000
1#
b11 $
1*
sHdlSome\x20(1) +
1,
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15f=Y~
#17500000
#17750000
0#
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#18000000
b10 !
b10 (
b10 xkkG>
b10 uabMI
#18250000
1#
b0 $
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#19000000
b0 !
b0 (
b0 xkkG>
b0 uabMI
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#19750000
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b1 !
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#21500000
#21750000
0#
0*
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0OpH)U
#22000000

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@ -1,47 +1,47 @@
$timescale 1 ps $end
$scope module mod1 $end
$scope struct o $end
$var wire 4 ! i $end
$var wire 2 " o $end
$var wire 2 # i2 $end
$var wire 4 $ o2 $end
$var wire 4 avK(^ i $end
$var wire 2 Q2~aG o $end
$var wire 2 DXK'| i2 $end
$var wire 4 cPuix o2 $end
$upscope $end
$scope struct child $end
$var wire 4 ) i $end
$var wire 2 * o $end
$var wire 2 + i2 $end
$var wire 4 , o2 $end
$var wire 4 ($5K7 i $end
$var wire 2 %6Wv" o $end
$var wire 2 +|-AU i2 $end
$var wire 4 Hw?%j o2 $end
$upscope $end
$scope module mod1_child $end
$var wire 4 % i $end
$var wire 2 & o $end
$var wire 2 ' i2 $end
$var wire 4 ( o2 $end
$var wire 4 4}s%= i $end
$var wire 2 }IY?g o $end
$var wire 2 of42K i2 $end
$var wire 4 D9]&= o2 $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
b11 !
b11 "
b10 #
b1110 $
b11 %
b11 &
b10 '
b1110 (
b11 )
b11 *
b10 +
b1110 ,
b11 avK(^
b11 Q2~aG
b10 DXK'|
b1110 cPuix
b11 4}s%=
b11 }IY?g
b10 of42K
b1110 D9]&=
b11 ($5K7
b11 %6Wv"
b10 +|-AU
b1110 Hw?%j
$end
#1000000
b1010 !
b10 "
b1111 $
b1010 %
b10 &
b1111 (
b1010 )
b10 *
b1111 ,
b1010 avK(^
b10 Q2~aG
b1111 cPuix
b1010 4}s%=
b10 }IY?g
b1111 D9]&=
b1010 ($5K7
b10 %6Wv"
b1111 Hw?%j
#2000000

View file

@ -1,31 +1,31 @@
$timescale 1 ps $end
$scope module phantom_const $end
$scope struct out $end
$var string 1 ! \[0] $end
$var string 1 " \[1] $end
$var string 1 Ru)8A \[0] $end
$var string 1 y&ssi \[1] $end
$upscope $end
$scope struct mem $end
$scope struct contents $end
$scope struct \[0] $end
$var string 1 ' mem $end
$var string 1 =+olp mem $end
$upscope $end
$upscope $end
$scope struct r0 $end
$var string 0 # addr $end
$var wire 1 $ en $end
$var wire 1 % clk $end
$var string 1 & data $end
$var string 0 U5SS1 addr $end
$var wire 1 rx@_T en $end
$var wire 1 o[(us clk $end
$var string 1 %Bg(6 data $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
s0 '
sPhantomConst([\"a\",\"b\"]) !
sPhantomConst([\"a\",\"b\"]) "
s0 #
0$
0%
sPhantomConst(\"mem_element\") &
s0 =+olp
sPhantomConst([\"a\",\"b\"]) Ru)8A
sPhantomConst([\"a\",\"b\"]) y&ssi
s0 U5SS1
0rx@_T
0o[(us
sPhantomConst(\"mem_element\") %Bg(6
$end
#1000000

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View file

@ -1,193 +1,193 @@
$timescale 1 ps $end
$scope module shift_register $end
$scope struct cd $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 1 <Ol<I clk $end
$var wire 1 ,E;9k rst $end
$upscope $end
$var wire 1 # d $end
$var wire 1 $ q $end
$var reg 1 % reg0 $end
$var reg 1 & reg1 $end
$var reg 1 ' reg2 $end
$var reg 1 ( reg3 $end
$var wire 1 %2/Zc d $end
$var wire 1 '1p#x q $end
$var reg 1 vd~J{ reg0 $end
$var reg 1 ~7wBy reg1 $end
$var reg 1 s@[|n reg2 $end
$var reg 1 %.BqD reg3 $end
$upscope $end
$enddefinitions $end
$dumpvars
0!
1"
0#
0$
0%
0&
0'
0(
0<Ol<I
1,E;9k
0%2/Zc
0'1p#x
0vd~J{
0~7wBy
0s@[|n
0%.BqD
$end
#1000000
1!
1<Ol<I
#1100000
0"
0,E;9k
#2000000
0!
0<Ol<I
#3000000
1!
1<Ol<I
#4000000
0!
1#
0<Ol<I
1%2/Zc
#5000000
1!
1%
1<Ol<I
1vd~J{
#6000000
0!
0<Ol<I
#7000000
1!
1&
1<Ol<I
1~7wBy
#8000000
0!
0#
0<Ol<I
0%2/Zc
#9000000
1!
0%
1'
1<Ol<I
0vd~J{
1s@[|n
#10000000
0!
0<Ol<I
#11000000
1!
1$
0&
1(
1<Ol<I
1'1p#x
0~7wBy
1%.BqD
#12000000
0!
1#
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1%2/Zc
#13000000
1!
1%
0'
1<Ol<I
1vd~J{
0s@[|n
#14000000
0!
0#
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#15000000
1!
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1&
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1<Ol<I
0'1p#x
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0%.BqD
#16000000
0!
1#
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1%2/Zc
#17000000
1!
1%
0&
1'
1<Ol<I
1vd~J{
0~7wBy
1s@[|n
#18000000
0!
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#19000000
1!
1$
1&
0'
1(
1<Ol<I
1'1p#x
1~7wBy
0s@[|n
1%.BqD
#20000000
0!
0<Ol<I
#21000000
1!
0$
1'
0(
1<Ol<I
0'1p#x
1s@[|n
0%.BqD
#22000000
0!
0<Ol<I
#23000000
1!
1$
1(
1<Ol<I
1'1p#x
1%.BqD
#24000000
0!
0#
0<Ol<I
0%2/Zc
#25000000
1!
0%
1<Ol<I
0vd~J{
#26000000
0!
0<Ol<I
#27000000
1!
0&
1<Ol<I
0~7wBy
#28000000
0!
0<Ol<I
#29000000
1!
0'
1<Ol<I
0s@[|n
#30000000
0!
0<Ol<I
#31000000
1!
0$
0(
1<Ol<I
0'1p#x
0%.BqD
#32000000
0!
0<Ol<I
#33000000
1!
1<Ol<I
#34000000
0!
0<Ol<I
#35000000
1!
1<Ol<I
#36000000
0!
0<Ol<I
#37000000
1!
1<Ol<I
#38000000
0!
0<Ol<I
#39000000
1!
1<Ol<I
#40000000
0!
0<Ol<I
#41000000
1!
1<Ol<I
#42000000
0!
0<Ol<I
#43000000
1!
1<Ol<I
#44000000
0!
0<Ol<I
#45000000
1!
1<Ol<I
#46000000
0!
0<Ol<I
#47000000
1!
1<Ol<I
#48000000
0!
0<Ol<I
#49000000
1!
1<Ol<I
#50000000
0!
0<Ol<I
#51000000
1!
1<Ol<I
#52000000
0!
0<Ol<I
#53000000
1!
1<Ol<I
#54000000
0!
0<Ol<I
#55000000
1!
1<Ol<I
#56000000
0!
0<Ol<I
#57000000
1!
1<Ol<I
#58000000
0!
0<Ol<I
#59000000
1!
1<Ol<I
#60000000
0!
0<Ol<I
#61000000
1!
1<Ol<I
#62000000
0!
0<Ol<I
#63000000
1!
1<Ol<I
#64000000
0!
0<Ol<I
#65000000
1!
1<Ol<I
#66000000

File diff suppressed because it is too large Load diff

File diff suppressed because it is too large Load diff

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@ -1,182 +1,182 @@
$timescale 1 ps $end
$scope module sim_only_connects $end
$scope struct cd $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 1 tq:(w clk $end
$var wire 1 FVlgb rst $end
$upscope $end
$var string 1 # inp $end
$var string 1 $ out1 $end
$var string 1 % out2 $end
$var string 1 & out3 $end
$var string 1 g:xf? inp $end
$var string 1 [OKKg out1 $end
$var string 1 9pB-> out2 $end
$var string 1 8(7-4 out3 $end
$scope struct helper1 $end
$scope struct cd $end
$var wire 1 + clk $end
$var wire 1 , rst $end
$var wire 1 $Kwp\ clk $end
$var wire 1 nmVq' rst $end
$upscope $end
$var string 1 - inp $end
$var string 1 . out $end
$var string 1 qS)@z inp $end
$var string 1 ~je// out $end
$upscope $end
$scope module sim_only_connects_helper $end
$scope struct cd $end
$var wire 1 ' clk $end
$var wire 1 ( rst $end
$var wire 1 %uCn6 clk $end
$var wire 1 Apu`K rst $end
$upscope $end
$var string 1 ) inp $end
$var string 1 * out $end
$var string 1 $U*lA inp $end
$var string 1 !prwC out $end
$upscope $end
$var string 1 / delay1 $end
$var reg 1 0 delay1_empty $end
$var string 1 CyjVm delay1 $end
$var reg 1 z~g{\ delay1_empty $end
$scope struct helper2 $end
$scope struct cd $end
$var wire 1 5 clk $end
$var wire 1 6 rst $end
$var wire 1 Ph.=# clk $end
$var wire 1 !GXK\ rst $end
$upscope $end
$var string 1 7 inp $end
$var string 1 8 out $end
$var string 1 /YVv: inp $end
$var string 1 Kk*{# out $end
$upscope $end
$scope module sim_only_connects_helper_2 $end
$scope struct cd $end
$var wire 1 1 clk $end
$var wire 1 2 rst $end
$var wire 1 %uCn6" clk $end
$var wire 1 Apu`K" rst $end
$upscope $end
$var string 1 3 inp $end
$var string 1 4 out $end
$var string 1 $U*lA" inp $end
$var string 1 !prwC" out $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
0!
1"
s{\"extra\":\x20\"value\"} #
s{} $
s{} %
s{} &
0'
1(
s{} )
s{} *
0+
1,
s{} -
s{} .
s{} /
00
01
12
s{} 3
s{} 4
05
16
s{} 7
s{} 8
0tq:(w
1FVlgb
s{\"extra\":\x20\"value\"} g:xf?
s{} [OKKg
s{} 9pB->
s{} 8(7-4
0%uCn6
1Apu`K
s{} $U*lA
s{} !prwC
0$Kwp\
1nmVq'
s{} qS)@z
s{} ~je//
s{} CyjVm
0z~g{\
0%uCn6"
1Apu`K"
s{} $U*lA"
s{} !prwC"
0Ph.=#
1!GXK\
s{} /YVv:
s{} Kk*{#
$end
#1000000
1!
s{\"extra\":\x20\"value\"} $
1'
s{\"extra\":\x20\"value\"} )
1+
s{\"extra\":\x20\"value\"} -
10
11
15
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} %
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} *
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} .
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 3
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 7
s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} &
s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 4
s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8
1tq:(w
s{\"extra\":\x20\"value\"} [OKKg
1%uCn6
s{\"extra\":\x20\"value\"} $U*lA
1$Kwp\
s{\"extra\":\x20\"value\"} qS)@z
1z~g{\
1%uCn6"
1Ph.=#
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 9pB->
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} !prwC
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} ~je//
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} $U*lA"
s{\"bar\":\x20\"\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} /YVv:
s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} 8(7-4
s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} !prwC"
s{\"bar\":\x20\"baz\",\x20\"extra\":\x20\"value\",\x20\"foo\":\x20\"baz\"} Kk*{#
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#16000000

File diff suppressed because it is too large Load diff

View file

@ -1,68 +1,68 @@
$timescale 1 ps $end
$scope module sim_resettable_counter $end
$scope struct cd $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 1 zGup) clk $end
$var wire 1 TfzI\ rst $end
$upscope $end
$var wire 8 # out $end
$var wire 8 #$b%i out $end
$upscope $end
$enddefinitions $end
$dumpvars
0!
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$end
#1000000
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b1 #
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b1 #$b%i
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#5000000
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b1 #$b%i
#6000000
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#7000000
1!
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b10 #$b%i
#8000000
0!
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#9000000
1!
b11 #
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b11 #$b%i
#10000000
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#11000000
1!
b100 #
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b100 #$b%i
#12000000
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#17000000
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b10 #$b%i
#18000000
0!
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#19000000
1!
b11 #
1zGup)
b11 #$b%i
#20000000
0!
0zGup)

View file

@ -1,65 +1,65 @@
$timescale 1 ps $end
$scope module sim_resettable_counter $end
$scope struct cd $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 1 zGup) clk $end
$var wire 1 TfzI\ rst $end
$upscope $end
$var wire 8 # out $end
$var wire 8 #$b%i out $end
$upscope $end
$enddefinitions $end
$dumpvars
0!
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$end
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b10 #$b%i
#8000000
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#9000000
1!
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b11 #$b%i
#10000000
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#11000000
1!
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b100 #$b%i
#12000000
0!
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1TfzI\
b0 #$b%i
#13000000
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#14000000
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#15000000
1!
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b1 #$b%i
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#17000000
1!
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b10 #$b%i
#18000000
0!
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#19000000
1!
b11 #
1zGup)
b11 #$b%i
#20000000
0!
0zGup)

View file

@ -1,70 +1,70 @@
$timescale 1 ps $end
$scope module sim_resettable_counter $end
$scope struct cd $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 1 zGup) clk $end
$var wire 1 TfzI\ rst $end
$upscope $end
$var wire 8 # out $end
$var wire 8 #$b%i out $end
$upscope $end
$enddefinitions $end
$dumpvars
0!
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$end
#1000000
1!
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b1 #$b%i
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b10 #$b%i
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#9000000
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b11 #$b%i
#10000000
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#11000000
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b1 #$b%i
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#17000000
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b10 #$b%i
#18000000
0!
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#19000000
1!
b11 #
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b11 #$b%i
#20000000
0!
0zGup)

View file

@ -1,70 +1,70 @@
$timescale 1 ps $end
$scope module sim_resettable_counter $end
$scope struct cd $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var wire 1 zGup) clk $end
$var wire 1 TfzI\ rst $end
$upscope $end
$var wire 8 # out $end
$var wire 8 #$b%i out $end
$upscope $end
$enddefinitions $end
$dumpvars
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$end
#1000000
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b1 #$b%i
b0 #$b%i
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#3000000
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b1 #$b%i
b0 #$b%i
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b1 #$b%i
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#7000000
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b10 #$b%i
#8000000
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#9000000
1!
b11 #
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b11 #$b%i
#10000000
0!
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#11000000
1!
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b100 #$b%i
#12000000
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b101 #$b%i
b0 #$b%i
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#15000000
1!
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b1 #$b%i
#16000000
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#17000000
1!
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b10 #$b%i
#18000000
0!
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#19000000
1!
b11 #
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b11 #$b%i
#20000000
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