Jacob Lifshay
fdc73b5f3b
add ripple counter test to test simulating alternating circuits and extern modules
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 4m19s
/ deps (push) Successful in 12s
/ test (push) Successful in 4m26s
2025-03-25 18:56:26 -07:00
Jacob Lifshay
a115585d5a
simulator: allow external module generators to wait for value changes and/or clock edges
/ deps (pull_request) Successful in 16s
/ test (pull_request) Successful in 4m2s
2025-03-25 18:26:48 -07:00
Jacob Lifshay
ab9ff4f2db
simplify setting an extern module simulation
/ deps (pull_request) Successful in 12m46s
/ test (pull_request) Successful in 4m8s
2025-03-21 17:08:29 -07:00
Jacob Lifshay
d1bd176b28
implement simulation of extern modules
/ deps (pull_request) Successful in 11m39s
/ test (pull_request) Successful in 3m55s
2025-03-21 01:47:14 -07:00
Jacob Lifshay
920d8d875f
add some missing #[track_caller]
2025-03-19 17:10:51 -07:00
Jacob Lifshay
d453755bb2
add ExprPartialEq/ExprPartialOrd impls for PhantomConst
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 3m45s
/ deps (push) Successful in 13s
/ test (push) Successful in 4m10s
2025-03-10 19:40:03 -07:00
Jacob Lifshay
450e1004b6
fix using fayalite as a dependency
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 3m51s
/ deps (push) Successful in 13s
/ test (push) Successful in 4m14s
2025-03-09 23:14:14 -07:00
Jacob Lifshay
c0c5b550bc
add PhantomConst
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 3m51s
/ deps (push) Successful in 13s
/ test (push) Successful in 4m15s
2025-03-09 21:03:47 -07:00
Jacob Lifshay
2fa0ea6192
make FillInDefaultedGenerics work with Sizes and not just Types
2025-03-09 20:59:21 -07:00
Jacob Lifshay
bd75fdfefd
add efficient prefix-sums and reductions
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 3m40s
/ deps (push) Successful in 14s
/ test (push) Successful in 4m5s
2025-03-02 23:04:17 -08:00
Jacob Lifshay
50c86e18dc
add Expr<ArrayType<T, Len>>: IntoIterator and Expr<Array<T>>: FromIterator<T>
/ deps (pull_request) Successful in 16s
/ test (pull_request) Successful in 3m40s
/ deps (push) Successful in 13s
/ test (push) Successful in 4m5s
2025-03-02 18:02:34 -08:00
Jacob Lifshay
60734cc9d1
switch CI to use mirrors
/ deps (pull_request) Successful in 12m27s
/ test (pull_request) Successful in 4m3s
/ deps (push) Successful in 14s
/ test (push) Successful in 4m14s
2025-03-02 17:43:29 -08:00
Jacob Lifshay
3458c21f44
add #[hdl(cmp_eq)] to implement HdlPartialEq automatically
/ deps (pull_request) Successful in 19s
/ test (pull_request) Successful in 3m38s
/ deps (push) Successful in 15s
/ test (push) Successful in 4m10s
2025-02-16 20:48:16 -08:00
Jacob Lifshay
43797db36e
sort custom keywords
2025-02-16 20:46:54 -08:00
Jacob Lifshay
cdd84953d0
support unknown trait bounds in type parameters
/ deps (pull_request) Successful in 19s
/ test (pull_request) Successful in 3m34s
/ deps (push) Successful in 14s
/ test (push) Successful in 3m58s
2025-02-13 18:35:30 -08:00
Jacob Lifshay
86a1bb46be
add #[hdl] let destructuring and, while at it, tuple patterns
/ deps (pull_request) Successful in 11m32s
/ test (pull_request) Successful in 3m44s
/ deps (push) Successful in 15s
/ test (push) Successful in 4m9s
2025-02-10 22:49:41 -08:00
Jacob Lifshay
209d5b5fe1
fix broken doc links
2025-02-10 22:49:16 -08:00
Jacob Lifshay
d4ea826051
sim: fix "label address not set" bug when the last Assignment is conditional
/ deps (pull_request) Successful in 23s
/ test (pull_request) Successful in 3m32s
/ deps (push) Successful in 15s
/ test (push) Successful in 3m58s
2025-01-15 19:04:40 -08:00
Jacob Lifshay
404a2ee043
tests/sim: add test_array_rw
/ deps (pull_request) Successful in 19s
/ test (pull_request) Successful in 3m34s
/ deps (push) Successful in 15s
/ test (push) Successful in 4m2s
2025-01-12 21:38:59 -08:00
Jacob Lifshay
e3a2ccd41c
properly handle duplicate names in vcd
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 3m43s
/ deps (push) Successful in 15s
/ test (push) Successful in 4m8s
2025-01-09 22:52:22 -08:00
Cesar Strauss
3771cea78e
Gather the FIFO debug ports in a bundle
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 3m35s
/ deps (push) Successful in 16s
/ test (push) Successful in 3m59s
2024-12-29 13:17:24 -03:00
Cesar Strauss
dcf865caec
Add assertions and debug ports in order for the FIFO to pass induction
...
As some proofs involving memories, it is necessary to add more ports to
the queue interface, to sync state. These changes are predicated on the
test environment, so normal use is not affected.
Since some speedup is achieved, use the saved time to test with a deeper
FIFO.
2024-12-29 13:12:58 -03:00
Cesar Strauss
31d01046a8
Initial queue formal proof based on one-entry FIFO equivalence
...
For now, only check that the basic properties work in bounded model check
mode, leave the induction proof for later.
Partially replace the previously existing proof.
Remove earlier assumptions and bounds that don't apply for this proof.
Use parameterized types instead of hard-coded types.
2024-12-29 13:04:01 -03:00
Jacob Lifshay
c16726cee6
fix #[hdl]/#[hdl_module] attributes getting the wrong hygiene when processing #[cfg]s
/ deps (pull_request) Successful in 17s
/ test (pull_request) Successful in 5m13s
/ deps (push) Successful in 14s
/ test (push) Successful in 5m42s
2024-12-29 00:48:15 -08:00
Jacob Lifshay
b63676d0ca
add test for cfgs
/ deps (pull_request) Successful in 18s
/ test (pull_request) Successful in 5m23s
/ deps (push) Successful in 14s
/ test (push) Successful in 6m5s
2024-12-28 23:39:50 -08:00
Jacob Lifshay
7005fa3330
implement handling #[cfg] and #[cfg_attr] in proc macro inputs
2024-12-28 23:39:08 -08:00
Jacob Lifshay
2ab8428062
upgrade syn version
2024-12-28 23:39:08 -08:00
Jacob Lifshay
9b06019bf5
make sim::Compiler not print things to stdout unless you ask for it
/ deps (pull_request) Successful in 16s
/ test (pull_request) Successful in 5m12s
/ deps (push) Successful in 16s
/ test (push) Successful in 5m18s
2024-12-18 21:15:09 -08:00
Jacob Lifshay
36bad52978
sim: fix sim.write to struct
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 5m16s
/ deps (push) Successful in 14s
/ test (push) Successful in 5m14s
2024-12-18 20:50:50 -08:00
Jacob Lifshay
21c73051ec
sim: add SimValue and reading/writing more than just a scalar
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 5m14s
/ deps (push) Successful in 14s
/ test (push) Successful in 5m12s
2024-12-18 01:39:35 -08:00
Jacob Lifshay
304d8da0e8
Merge remote-tracking branch 'origin/master' into adding-simulator
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 5m24s
/ deps (push) Successful in 16s
/ test (push) Successful in 5m46s
2024-12-13 15:06:45 -08:00
Jacob Lifshay
2af38de900
add more memory tests
/ deps (push) Successful in 19s
/ test (push) Has been cancelled
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 5m21s
2024-12-13 15:04:48 -08:00
Jacob Lifshay
c756aeec70
tests/sim: add test for memory rw port
/ deps (push) Successful in 18s
/ test (push) Successful in 5m20s
/ deps (pull_request) Successful in 13s
/ test (pull_request) Successful in 6m32s
2024-12-12 20:50:41 -08:00
Jacob Lifshay
903ca1bf30
sim: simple memory test works!
/ deps (push) Successful in 17s
/ test (push) Successful in 5m20s
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 5m24s
2024-12-12 19:47:57 -08:00
Jacob Lifshay
8d030ac65d
sim/interpreter: add addresses to instruction listing
/ deps (push) Successful in 18s
/ test (push) Successful in 5m20s
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 5m19s
2024-12-12 16:25:38 -08:00
Jacob Lifshay
562c479b62
sim/interpreter: fix StatePartLayout name in debug output
2024-12-12 15:06:17 -08:00
Jacob Lifshay
393f78a14d
sim: add WIP memory test
/ deps (push) Successful in 18s
/ test (push) Successful in 5m16s
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 5m19s
2024-12-11 23:28:15 -08:00
Jacob Lifshay
8616ee4737
tests/sim: test_enums works!
/ deps (push) Successful in 17s
/ test (push) Successful in 5m18s
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 5m20s
2024-12-11 00:01:04 -08:00
Jacob Lifshay
5087f16099
sim: fix assignments graph by properly including conditions as assignment inputs
2024-12-11 00:00:21 -08:00
Jacob Lifshay
6b31e6d515
sim: add .dot output for Assignments graph for debugging
/ deps (push) Successful in 18s
/ test (push) Successful in 5m20s
/ deps (pull_request) Successful in 15s
/ test (pull_request) Successful in 5m21s
2024-12-10 23:40:33 -08:00
Jacob Lifshay
564ccb30bc
sim/vcd: fix variable identifiers to follow verilog rules
2024-12-10 23:39:17 -08:00
Jacob Lifshay
ca759168ff
tests/sim: add WIP test for enums
2024-12-10 23:37:26 -08:00
Jacob Lifshay
e4cf66adf8
sim: implement memories, still needs testing
/ deps (push) Successful in 18s
/ test (push) Successful in 5m15s
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 5m20s
2024-12-09 23:03:01 -08:00
Jacob Lifshay
cd0dd7b7ee
change memory write latency to NonZeroUsize to match read latency being usize
2024-12-09 23:01:40 -08:00
Cesar Strauss
2e7d685dc7
add module exercising formal verification of memories
/ deps (pull_request) Successful in 11m25s
/ test (pull_request) Successful in 4m47s
/ deps (push) Successful in 14s
/ test (push) Successful in 5m12s
2024-12-08 17:13:26 -03:00
Jacob Lifshay
9654167ca3
sim: WIP working on memory
/ deps (push) Successful in 17s
/ test (push) Successful in 5m18s
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 5m18s
2024-12-06 15:53:34 -08:00
Jacob Lifshay
3ed7827485
sim: WIP adding memory support
/ deps (push) Successful in 16s
/ test (push) Successful in 5m28s
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 5m24s
2024-12-05 21:35:23 -08:00
Jacob Lifshay
e504cfebfe
add BoolOrIntType::copy_bits_from_bigint_wrapping and take BigInt arguments by reference
/ deps (push) Successful in 17s
/ test (push) Successful in 5m21s
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 5m19s
2024-12-05 20:32:15 -08:00
Jacob Lifshay
9f42cab471
change to version 0.3.0 for breaking change
2024-12-05 20:26:28 -08:00
Jacob Lifshay
259bee39c2
tests/sim: split expected output text into separate files
/ deps (push) Successful in 18s
/ test (push) Successful in 5m16s
/ deps (pull_request) Successful in 14s
/ test (pull_request) Successful in 5m22s
2024-12-05 18:17:13 -08:00
Jacob Lifshay
Cesar Strauss
