|
|
a398f8f185
|
Define design safety, and prove it for 1-step and 2-step induction.
/ test (pull_request) Successful in 4m8s
/ test (push) Successful in 4m35s
|
2025-12-22 22:30:13 -03:00 |
|
|
|
4fd4371054
|
Spelling.
|
2025-12-22 22:30:06 -03:00 |
|
|
|
c97b44d9d6
|
simplify SimValue Debug format, making complex structures much easier to read
/ test (pull_request) Successful in 3m55s
/ test (push) Successful in 4m30s
|
2025-12-14 20:59:48 -08:00 |
|
|
|
fbe4585578
|
add FillInDefaultedGenerics<Type = Self> bound for SizeType
/ test (pull_request) Successful in 3m56s
/ test (push) Successful in 4m26s
|
2025-12-10 20:10:39 -08:00 |
|
|
|
e4210a672f
|
Check copyright header in Rocq files.
/ test (pull_request) Successful in 4m4s
/ test (push) Successful in 4m39s
If we ever add Verilog files, we can "or" both results, I guess.
|
2025-12-09 07:45:35 -03:00 |
|
|
|
e54558d848
|
Demonstrates state with multiple variables and hidden state.
/ test (pull_request) Failing after 22s
|
2025-12-08 22:00:49 -03:00 |
|
|
|
46f3519c76
|
Demonstrate a preliminary mapping from HDL to Rocq.
Starts with a very simple example, including a proof by induction.
|
2025-12-08 19:32:05 -03:00 |
|
|
|
9e803223d0
|
support operations directly on SimValue, UIntValue, and SIntValue, and shared references to those
/ test (pull_request) Successful in 3m59s
/ test (push) Successful in 4m38s
|
2025-11-24 00:14:53 -08:00 |
|
|
|
2a65aa2bd5
|
fix DynShr[SU]'s literal bits to properly shift right instead of left
|
2025-11-20 02:25:05 -08:00 |
|
|
|
2817cd3d58
|
support Rust's default binding modes when destructuring with #[hdl(sim)] let/match
/ test (pull_request) Successful in 4m47s
/ test (push) Successful in 5m25s
|
2025-11-14 00:20:54 -08:00 |
|
|
|
053c1b2b10
|
implement Display for SimValue<T>
|
2025-11-14 00:20:54 -08:00 |
|
|
|
17b58e8edb
|
add utility impls for SimValue<ArrayType<_, _>>
/ test (pull_request) Successful in 4m52s
/ test (push) Successful in 5m28s
|
2025-11-13 20:21:07 -08:00 |
|
|
|
df020e9c9b
|
add ExternModuleSimulatorState::read_past() and more output when simulator trace is enabled
/ test (pull_request) Successful in 4m52s
/ test (push) Successful in 5m28s
|
2025-11-12 22:31:45 -08:00 |
|
|
|
45fea70c18
|
add ExternModuleSimulationState::fork_join_scope
/ test (pull_request) Successful in 4m47s
/ test (push) Successful in 5m24s
|
2025-11-07 02:18:43 -08:00 |
|
|
|
fbc8ffa5ae
|
fix private fields in #[hdl] pub struct
/ test (pull_request) Successful in 4m53s
/ test (push) Successful in 5m38s
|
2025-11-06 20:23:16 -08:00 |
|
|
|
26a7090178
|
add ParsedVisibility
|
2025-11-06 20:22:53 -08:00 |
|
|
|
0b77d1bea0
|
fix Simulator panicking when you use PhantomConst
/ test (pull_request) Successful in 5m2s
/ test (push) Successful in 5m38s
|
2025-11-05 22:44:43 -08:00 |
|
|
|
840c5e1895
|
add ExternModuleSimulationState::resettable helper for procedural simulations that have a reset input.
/ test (pull_request) Successful in 4m55s
/ test (push) Successful in 5m31s
|
2025-11-03 23:59:36 -08:00 |
|
|
|
c11a1743f9
|
add sim.fork_join() and fix Simulator to handle running futures with arbitrary wakers
/ test (pull_request) Successful in 4m51s
/ test (push) Successful in 5m29s
|
2025-10-30 21:16:05 -07:00 |
|
|
|
0be9f9ce23
|
fix JobGraph::run to not busy-wait
/ test (pull_request) Successful in 4m50s
/ test (push) Successful in 5m27s
|
2025-10-27 22:57:12 -07:00 |
|
|
|
0b82178740
|
add PhantomConstGet to the known Type bounds for #[hdl] struct/enum
/ test (pull_request) Successful in 4m54s
/ test (push) Successful in 5m28s
|
2025-10-27 20:08:22 -07:00 |
|
|
|
4b24a88641
|
add docs for #[hdl] and particularly for #[hdl] type aliases
/ test (pull_request) Successful in 4m50s
/ test (push) Successful in 5m26s
|
2025-10-26 03:25:35 -07:00 |
|
|
|
094c77e26e
|
add #[hdl(get(|v| ...))] type GetStuff<P: PhantomConstGet<MyStruct>> = MyType or DynSize;
|
2025-10-26 03:25:35 -07:00 |
|
|
|
d2c8b023bf
|
deny broken docs
|
2025-10-26 03:25:35 -07:00 |
|
|
|
c043ee54d0
|
fix rustdoc warning for link in readme
|
2025-10-26 03:25:35 -07:00 |
|
|
|
edcc5927a5
|
don't cache external job failures if they could be caused by the user killing processes
/ test (pull_request) Successful in 4m51s
/ test (push) Successful in 5m30s
|
2025-10-24 02:27:20 -07:00 |
|
|
|
7dc4417874
|
add test_many_memories so we catch if memories are iterated in an inconsistent order like in 838bd469ce
/ test (pull_request) Successful in 4m44s
/ test (push) Successful in 5m22s
|
2025-10-24 01:40:30 -07:00 |
|
|
|
838bd469ce
|
change SimulationImpl::trace_memories to a BTreeMap for consistent iteration order
|
2025-10-24 00:53:13 -07:00 |
|
|
|
b6e4cd0614
|
move FormalMode to crate::testing and add to prelude
|
2025-10-24 00:14:04 -07:00 |
|
|
|
3e5b2f126a
|
make UIntInRange[Inclusive][Type] castable from/to any UInt<N> and add methods to get bit_width, start, and end
|
2025-10-23 23:52:41 -07:00 |
|
|
|
040cefea21
|
add tx_only_uart example to readme
/ test (pull_request) Successful in 4m43s
/ test (push) Successful in 5m21s
|
2025-10-22 20:31:25 -07:00 |
|
|
|
3267cb38c4
|
build tx_only_uart in CI
/ test (pull_request) Successful in 4m41s
|
2025-10-22 20:12:08 -07:00 |
|
|
|
b3cc28e2b6
|
add transmit-only UART example
/ test (pull_request) Successful in 4m33s
|
2025-10-22 20:11:02 -07:00 |
|
|
|
26840daf13
|
arty_a7: add divided clocks as available input peripherals so you're not stuck with 100MHz
|
2025-10-22 20:11:02 -07:00 |
|
|
|
4d9e8d3b47
|
Add building blinky example to the readme
/ test (pull_request) Successful in 4m31s
/ test (push) Successful in 5m9s
|
2025-10-21 23:00:16 -07:00 |
|
|
|
c6feea6d51
|
properly handle all XilinxAnnotations, this makes nextpnr-xilinx properly pick up the clock frequency
/ test (pull_request) Successful in 4m34s
/ test (push) Successful in 5m9s
|
2025-10-21 22:24:02 -07:00 |
|
|
|
409992961c
|
switch to using verilog for reset synchronizer so we can use attributes on FDPE instances
|
2025-10-21 22:24:02 -07:00 |
|
|
|
2bdc8a7c72
|
WIP adding xdc create_clock -- nextpnr-xilinx currently ignores it
/ test (pull_request) Successful in 4m35s
|
2025-10-19 23:13:28 -07:00 |
|
|
|
477a1f2d29
|
Add peripherals and Arty A7 platforms -- blinky works correctly now on arty-a7-100t!
|
2025-10-19 23:13:28 -07:00 |
|
|
|
4d54f903be
|
move vendor module to top level
|
2025-10-17 15:00:19 -07:00 |
|
|
|
3f5dd61e46
|
WIP adding Platform
/ test (pull_request) Successful in 4m28s
|
2025-10-17 05:55:22 -07:00 |
|
|
|
def406ab52
|
group all xilinx annotations together
/ test (pull_request) Successful in 4m23s
|
2025-10-16 04:53:58 -07:00 |
|
|
|
a565be1b09
|
do some clean up
/ test (pull_request) Successful in 4m24s
|
2025-10-16 04:32:56 -07:00 |
|
|
|
676c1e3b7d
|
WIP adding annotations for generating the .xdc file for yosys-nextpnr-prjxray
/ test (pull_request) Successful in 4m27s
|
2025-10-15 04:29:00 -07:00 |
|
|
|
169be960f8
|
generate Arty A7 100T .bit file for blinky example in CI
|
2025-10-15 04:29:00 -07:00 |
|
|
|
2b52799f5c
|
try building .bit file
|
2025-10-15 04:29:00 -07:00 |
|
|
|
35f98f3229
|
fix redirects
|
2025-10-15 04:29:00 -07:00 |
|
|
|
8a63ea89d0
|
WIP adding yosys-nextpnr-xray xilinx fpga toolchain -- blinky works on arty a7 100t (except for inverted reset)
|
2025-10-15 04:29:00 -07:00 |
|
|
|
84c5978eaf
|
WIP build Xilinx FPGA dependencies in CI
|
2025-10-15 04:29:00 -07:00 |
|
|
|
42e3179a60
|
change cache directory name to be fayalite-specific
|
2025-10-15 04:29:00 -07:00 |
|
