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add test that simulator handles last-connect semantics properly

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This commit is contained in:
Jacob Lifshay 2026-03-24 23:28:37 -07:00
parent a8a541b357
commit a0b2dc085c
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
3 changed files with 875 additions and 0 deletions
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70
crates/fayalite/tests/sim.rs
View file

@ -2495,3 +2495,73 @@ fn test_sim_read_past() {
panic!();
}
}
#[hdl_module(outline_generated)]
pub fn last_connect() {
#[hdl]
let inp: HdlOption<Array<Bool, 4>> = m.input();
#[hdl]
let out: HdlOption<UInt<8>> = m.output();
connect(out, HdlNone());
#[hdl]
if let HdlSome(v) = inp {
#[hdl]
let w = wire();
connect(out, HdlSome(w));
connect(w, v.len() as u8);
for (i, v) in v.into_iter().enumerate() {
#[hdl]
if v {
connect(w, i as u8);
}
}
}
}
#[hdl]
#[test]
fn test_last_connect() {
let _n = SourceLocation::normalize_files_for_tests();
let mut sim = Simulation::new(last_connect());
let mut writer = RcWriter::default();
sim.add_trace_writer(VcdWriterDecls::new(writer.clone()));
let bools = [false, true];
sim.write(sim.io().inp, HdlNone());
sim.advance_time(SimDuration::from_micros(1));
let expected: SimValue<HdlOption<UInt<8>>> = #[hdl(sim)]
HdlNone();
assert_eq!(sim.read(sim.io().out), expected);
for a in bools {
for b in bools {
for c in bools {
for d in bools {
let inp = [a, b, c, d];
sim.write(sim.io().inp, HdlSome(inp));
sim.advance_time(SimDuration::from_micros(1));
let mut expected = inp.len() as u8;
for (i, v) in inp.into_iter().enumerate() {
if v {
expected = i as u8;
}
}
let expected: SimValue<HdlOption<UInt<8>>> = #[hdl(sim)]
HdlSome(expected);
let out = sim.read(sim.io().out);
println!("expected={expected:?} out={out:?} inp={inp:?}");
assert_eq!(expected, out);
}
}
}
}
sim.flush_traces().unwrap();
let vcd = String::from_utf8(writer.take()).unwrap();
println!("####### VCD:\n{vcd}\n#######");
if vcd != include_str!("sim/expected/last_connect.vcd") {
panic!();
}
let sim_debug = format!("{sim:#?}");
println!("#######\n{sim_debug}\n#######");
if sim_debug != include_str!("sim/expected/last_connect.txt") {
panic!();
}
}

701
crates/fayalite/tests/sim/expected/last_connect.txt Normal file
View file

@ -0,0 +1,701 @@
Simulation {
state: State {
insns: Insns {
state_layout: StateLayout {
ty: TypeLayout {
small_slots: StatePartLayout<SmallSlots> {
len: 2,
debug_data: [
SlotDebugData {
name: "",
ty: Enum {
HdlNone,
HdlSome,
},
},
SlotDebugData {
name: "",
ty: Enum {
HdlNone,
HdlSome,
},
},
],
..
},
big_slots: StatePartLayout<BigSlots> {
len: 33,
debug_data: [
SlotDebugData {
name: "InstantiatedModule(last_connect: last_connect).last_connect::inp",
ty: Enum {
HdlNone,
HdlSome(Array<Bool, 4>),
},
},
SlotDebugData {
name: "[0]",
ty: Bool,
},
SlotDebugData {
name: "[1]",
ty: Bool,
},
SlotDebugData {
name: "[2]",
ty: Bool,
},
SlotDebugData {
name: "[3]",
ty: Bool,
},
SlotDebugData {
name: "",
ty: UInt<5>,
},
SlotDebugData {
name: "",
ty: UInt<4>,
},
SlotDebugData {
name: "",
ty: UInt<1>,
},
SlotDebugData {
name: "",
ty: Bool,
},
SlotDebugData {
name: "",
ty: UInt<1>,
},
SlotDebugData {
name: "",
ty: Bool,
},
SlotDebugData {
name: "",
ty: UInt<1>,
},
SlotDebugData {
name: "",
ty: Bool,
},
SlotDebugData {
name: "",
ty: UInt<1>,
},
SlotDebugData {
name: "",
ty: Bool,
},
SlotDebugData {
name: "InstantiatedModule(last_connect: last_connect).last_connect::out",
ty: Enum {
HdlNone,
HdlSome(UInt<8>),
},
},
SlotDebugData {
name: "",
ty: UInt<9>,
},
SlotDebugData {
name: "",
ty: UInt<8>,
},
SlotDebugData {
name: "",
ty: UInt<9>,
},
SlotDebugData {
name: "",
ty: Enum {
HdlNone,
HdlSome(UInt<8>),
},
},
SlotDebugData {
name: "InstantiatedModule(last_connect: last_connect).last_connect::w",
ty: UInt<8>,
},
SlotDebugData {
name: ".0",
ty: UInt<1>,
},
SlotDebugData {
name: ".1",
ty: UInt<8>,
},
SlotDebugData {
name: "",
ty: UInt<1>,
},
SlotDebugData {
name: "",
ty: UInt<9>,
},
SlotDebugData {
name: "",
ty: UInt<9>,
},
SlotDebugData {
name: "",
ty: UInt<9>,
},
SlotDebugData {
name: "",
ty: Enum {
HdlNone,
HdlSome(UInt<8>),
},
},
SlotDebugData {
name: "",
ty: UInt<8>,
},
SlotDebugData {
name: "",
ty: UInt<8>,
},
SlotDebugData {
name: "",
ty: UInt<8>,
},
SlotDebugData {
name: "",
ty: UInt<8>,
},
SlotDebugData {
name: "",
ty: UInt<8>,
},
],
..
},
sim_only_slots: StatePartLayout<SimOnlySlots> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
memories: StatePartLayout<Memories> {
len: 0,
debug_data: [],
layout_data: [],
..
},
},
insns: [
// at: module-XXXXXXXXXX.rs:1:1
0: Const {
dest: StatePartIndex<BigSlots>(32), // (0x3) SlotDebugData { name: "", ty: UInt<8> },
value: 0x3,
},
1: Const {
dest: StatePartIndex<BigSlots>(31), // (0x2) SlotDebugData { name: "", ty: UInt<8> },
value: 0x2,
},
2: Const {
dest: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: UInt<8> },
value: 0x1,
},
3: Const {
dest: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<8> },
value: 0x0,
},
4: Const {
dest: StatePartIndex<BigSlots>(28), // (0x4) SlotDebugData { name: "", ty: UInt<8> },
value: 0x4,
},
// at: module-XXXXXXXXXX.rs:8:1
5: Copy {
dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
src: StatePartIndex<BigSlots>(28), // (0x4) SlotDebugData { name: "", ty: UInt<8> },
},
// at: module-XXXXXXXXXX.rs:1:1
6: Const {
dest: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
value: 0x1,
},
7: Const {
dest: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<9> },
value: 0x0,
},
8: Copy {
dest: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
src: StatePartIndex<BigSlots>(18), // (0x0) SlotDebugData { name: "", ty: UInt<9> },
},
// at: module-XXXXXXXXXX.rs:4:1
9: Copy {
dest: StatePartIndex<BigSlots>(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
src: StatePartIndex<BigSlots>(19), // (0x0) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
},
// at: module-XXXXXXXXXX.rs:1:1
10: Copy {
dest: StatePartIndex<BigSlots>(5), // (0x1f) SlotDebugData { name: "", ty: UInt<5> },
src: StatePartIndex<BigSlots>(0), // (0x1f) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::inp", ty: Enum {HdlNone, HdlSome(Array<Bool, 4>)} },
},
11: SliceInt {
dest: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
src: StatePartIndex<BigSlots>(5), // (0x1f) SlotDebugData { name: "", ty: UInt<5> },
start: 1,
len: 4,
},
12: SliceInt {
dest: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
start: 0,
len: 1,
},
13: Copy {
dest: StatePartIndex<BigSlots>(8), // (0x1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(7), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
},
14: SliceInt {
dest: StatePartIndex<BigSlots>(9), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
start: 1,
len: 1,
},
15: Copy {
dest: StatePartIndex<BigSlots>(10), // (0x1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(9), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
},
16: SliceInt {
dest: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
start: 2,
len: 1,
},
17: Copy {
dest: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(11), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
},
18: SliceInt {
dest: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
src: StatePartIndex<BigSlots>(6), // (0xf) SlotDebugData { name: "", ty: UInt<4> },
start: 3,
len: 1,
},
19: Copy {
dest: StatePartIndex<BigSlots>(14), // (0x1) SlotDebugData { name: "", ty: Bool },
src: StatePartIndex<BigSlots>(13), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
},
20: Copy {
dest: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "[0]", ty: Bool },
src: StatePartIndex<BigSlots>(8), // (0x1) SlotDebugData { name: "", ty: Bool },
},
21: Copy {
dest: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "[1]", ty: Bool },
src: StatePartIndex<BigSlots>(10), // (0x1) SlotDebugData { name: "", ty: Bool },
},
22: Copy {
dest: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "[2]", ty: Bool },
src: StatePartIndex<BigSlots>(12), // (0x1) SlotDebugData { name: "", ty: Bool },
},
23: Copy {
dest: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "[3]", ty: Bool },
src: StatePartIndex<BigSlots>(14), // (0x1) SlotDebugData { name: "", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:9:1
24: BranchIfZero {
target: 26,
value: StatePartIndex<BigSlots>(1), // (0x1) SlotDebugData { name: "[0]", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:10:1
25: Copy {
dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
src: StatePartIndex<BigSlots>(29), // (0x0) SlotDebugData { name: "", ty: UInt<8> },
},
// at: module-XXXXXXXXXX.rs:9:1
26: BranchIfZero {
target: 28,
value: StatePartIndex<BigSlots>(2), // (0x1) SlotDebugData { name: "[1]", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:10:1
27: Copy {
dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
src: StatePartIndex<BigSlots>(30), // (0x1) SlotDebugData { name: "", ty: UInt<8> },
},
// at: module-XXXXXXXXXX.rs:9:1
28: BranchIfZero {
target: 30,
value: StatePartIndex<BigSlots>(3), // (0x1) SlotDebugData { name: "[2]", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:10:1
29: Copy {
dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
src: StatePartIndex<BigSlots>(31), // (0x2) SlotDebugData { name: "", ty: UInt<8> },
},
// at: module-XXXXXXXXXX.rs:9:1
30: BranchIfZero {
target: 32,
value: StatePartIndex<BigSlots>(4), // (0x1) SlotDebugData { name: "[3]", ty: Bool },
},
// at: module-XXXXXXXXXX.rs:10:1
31: Copy {
dest: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
src: StatePartIndex<BigSlots>(32), // (0x3) SlotDebugData { name: "", ty: UInt<8> },
},
// at: module-XXXXXXXXXX.rs:1:1
32: Copy {
dest: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
src: StatePartIndex<BigSlots>(23), // (0x1) SlotDebugData { name: "", ty: UInt<1> },
},
33: Copy {
dest: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: ".1", ty: UInt<8> },
src: StatePartIndex<BigSlots>(20), // (0x3) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::w", ty: UInt<8> },
},
34: Shl {
dest: StatePartIndex<BigSlots>(24), // (0x6) SlotDebugData { name: "", ty: UInt<9> },
lhs: StatePartIndex<BigSlots>(22), // (0x3) SlotDebugData { name: ".1", ty: UInt<8> },
rhs: 1,
},
35: Or {
dest: StatePartIndex<BigSlots>(25), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
lhs: StatePartIndex<BigSlots>(21), // (0x1) SlotDebugData { name: ".0", ty: UInt<1> },
rhs: StatePartIndex<BigSlots>(24), // (0x6) SlotDebugData { name: "", ty: UInt<9> },
},
36: CastToUInt {
dest: StatePartIndex<BigSlots>(26), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
src: StatePartIndex<BigSlots>(25), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
dest_width: 9,
},
37: Copy {
dest: StatePartIndex<BigSlots>(27), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
src: StatePartIndex<BigSlots>(26), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
},
// at: module-XXXXXXXXXX.rs:2:1
38: AndBigWithSmallImmediate {
dest: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
lhs: StatePartIndex<BigSlots>(0), // (0x1f) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::inp", ty: Enum {HdlNone, HdlSome(Array<Bool, 4>)} },
rhs: 0x1,
},
// at: module-XXXXXXXXXX.rs:5:1
39: BranchIfSmallNeImmediate {
target: 41,
lhs: StatePartIndex<SmallSlots>(0), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
rhs: 0x1,
},
// at: module-XXXXXXXXXX.rs:7:1
40: Copy {
dest: StatePartIndex<BigSlots>(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
src: StatePartIndex<BigSlots>(27), // (0x7) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
},
// at: module-XXXXXXXXXX.rs:3:1
41: AndBigWithSmallImmediate {
dest: StatePartIndex<SmallSlots>(1), // (0x1 1) SlotDebugData { name: "", ty: Enum {HdlNone, HdlSome} },
lhs: StatePartIndex<BigSlots>(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
rhs: 0x1,
},
// at: module-XXXXXXXXXX.rs:1:1
42: Copy {
dest: StatePartIndex<BigSlots>(16), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
src: StatePartIndex<BigSlots>(15), // (0x7) SlotDebugData { name: "InstantiatedModule(last_connect: last_connect).last_connect::out", ty: Enum {HdlNone, HdlSome(UInt<8>)} },
},
43: SliceInt {
dest: StatePartIndex<BigSlots>(17), // (0x3) SlotDebugData { name: "", ty: UInt<8> },
src: StatePartIndex<BigSlots>(16), // (0x7) SlotDebugData { name: "", ty: UInt<9> },
start: 1,
len: 8,
},
44: Return,
],
..
},
pc: 44,
memory_write_log: [],
memories: StatePart {
value: [],
},
small_slots: StatePart {
value: [
1,
1,
],
},
big_slots: StatePart {
value: [
31,
1,
1,
1,
1,
31,
15,
1,
1,
1,
1,
1,
1,
1,
1,
7,
7,
3,
0,
0,
3,
1,
3,
1,
6,
7,
7,
7,
4,
0,
1,
2,
3,
],
},
sim_only_slots: StatePart {
value: [],
},
},
io: Instance {
name: <simulator>::last_connect,
instantiated: Module {
name: last_connect,
..
},
},
main_module: SimulationModuleState {
base_targets: [
Instance {
name: <simulator>::last_connect,
instantiated: Module {
name: last_connect,
..
},
}.inp,
Instance {
name: <simulator>::last_connect,
instantiated: Module {
name: last_connect,
..
},
}.out,
],
uninitialized_ios: {},
io_targets: {
Instance {
name: <simulator>::last_connect,
instantiated: Module {
name: last_connect,
..
},
}.inp,
Instance {
name: <simulator>::last_connect,
instantiated: Module {
name: last_connect,
..
},
}.out,
},
did_initial_settle: true,
clocks_for_past: {},
},
extern_modules: [],
trace_decls: TraceModule {
name: "last_connect",
children: [
TraceModuleIO {
name: "inp",
child: TraceEnumWithFields {
name: "inp",
discriminant: TraceEnumDiscriminant {
location: TraceScalarId(0),
name: "$tag",
ty: Enum {
HdlNone,
HdlSome(Array<Bool, 4>),
},
flow: Source,
},
non_empty_fields: [
TraceArray {
name: "HdlSome",
elements: [
TraceBool {
location: TraceScalarId(1),
name: "[0]",
flow: Source,
},
TraceBool {
location: TraceScalarId(2),
name: "[1]",
flow: Source,
},
TraceBool {
location: TraceScalarId(3),
name: "[2]",
flow: Source,
},
TraceBool {
location: TraceScalarId(4),
name: "[3]",
flow: Source,
},
],
ty: Array<Bool, 4>,
flow: Source,
},
],
ty: Enum {
HdlNone,
HdlSome(Array<Bool, 4>),
},
flow: Source,
},
ty: Enum {
HdlNone,
HdlSome(Array<Bool, 4>),
},
flow: Source,
},
TraceModuleIO {
name: "out",
child: TraceEnumWithFields {
name: "out",
discriminant: TraceEnumDiscriminant {
location: TraceScalarId(5),
name: "$tag",
ty: Enum {
HdlNone,
HdlSome(UInt<8>),
},
flow: Sink,
},
non_empty_fields: [
TraceUInt {
location: TraceScalarId(6),
name: "HdlSome",
ty: UInt<8>,
flow: Source,
},
],
ty: Enum {
HdlNone,
HdlSome(UInt<8>),
},
flow: Sink,
},
ty: Enum {
HdlNone,
HdlSome(UInt<8>),
},
flow: Sink,
},
TraceWire {
name: "w",
child: TraceUInt {
location: TraceScalarId(7),
name: "w",
ty: UInt<8>,
flow: Duplex,
},
ty: UInt<8>,
},
],
},
traces: [
SimTrace {
id: TraceScalarId(0),
kind: EnumDiscriminant {
index: StatePartIndex<SmallSlots>(0),
ty: Enum {
HdlNone,
HdlSome(Array<Bool, 4>),
},
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(1),
kind: BigBool {
index: StatePartIndex<BigSlots>(1),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(2),
kind: BigBool {
index: StatePartIndex<BigSlots>(2),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(3),
kind: BigBool {
index: StatePartIndex<BigSlots>(3),
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(4),
kind: BigBool {
index: StatePartIndex<BigSlots>(4),
},
state: 0x1,
last_state: 0x0,
},
SimTrace {
id: TraceScalarId(5),
kind: EnumDiscriminant {
index: StatePartIndex<SmallSlots>(1),
ty: Enum {
HdlNone,
HdlSome(UInt<8>),
},
},
state: 0x1,
last_state: 0x1,
},
SimTrace {
id: TraceScalarId(6),
kind: BigUInt {
index: StatePartIndex<BigSlots>(17),
ty: UInt<8>,
},
state: 0x03,
last_state: 0x02,
},
SimTrace {
id: TraceScalarId(7),
kind: BigUInt {
index: StatePartIndex<BigSlots>(20),
ty: UInt<8>,
},
state: 0x03,
last_state: 0x02,
},
],
trace_memories: {},
trace_writers: [
Running(
VcdWriter {
finished_init: true,
timescale: 1 ps,
..
},
),
],
clocks_triggered: [],
event_queue: EventQueue(EventQueueData {
instant: 17 μs,
events: {},
}),
waiting_sensitivity_sets_by_address: {},
waiting_sensitivity_sets_by_compiled_value: {},
..
}

104
crates/fayalite/tests/sim/expected/last_connect.vcd Normal file
View file

@ -0,0 +1,104 @@
$timescale 1 ps $end
$scope module last_connect $end
$scope struct inp $end
$var string 1 !C&}* \$tag $end
$scope struct HdlSome $end
$var wire 1 D_viZ \[0] $end
$var wire 1 b5gFK \[1] $end
$var wire 1 xUBRH \[2] $end
$var wire 1 Gp7Xm \[3] $end
$upscope $end
$upscope $end
$scope struct out $end
$var string 1 ^Z_p3 \$tag $end
$var wire 8 rz~), HdlSome $end
$upscope $end
$var wire 8 dlea> w $end
$upscope $end
$enddefinitions $end
$dumpvars
sHdlNone\x20(0) !C&}*
0D_viZ
0b5gFK
0xUBRH
0Gp7Xm
sHdlNone\x20(0) ^Z_p3
b0 rz~),
b100 dlea>
$end
#1000000
sHdlSome\x20(1) !C&}*
sHdlSome\x20(1) ^Z_p3
b100 rz~),
#2000000
1Gp7Xm
b11 rz~),
b11 dlea>
#3000000
1xUBRH
0Gp7Xm
b10 rz~),
b10 dlea>
#4000000
1Gp7Xm
b11 rz~),
b11 dlea>
#5000000
1b5gFK
0xUBRH
0Gp7Xm
b1 rz~),
b1 dlea>
#6000000
1Gp7Xm
b11 rz~),
b11 dlea>
#7000000
1xUBRH
0Gp7Xm
b10 rz~),
b10 dlea>
#8000000
1Gp7Xm
b11 rz~),
b11 dlea>
#9000000
1D_viZ
0b5gFK
0xUBRH
0Gp7Xm
b0 rz~),
b0 dlea>
#10000000
1Gp7Xm
b11 rz~),
b11 dlea>
#11000000
1xUBRH
0Gp7Xm
b10 rz~),
b10 dlea>
#12000000
1Gp7Xm
b11 rz~),
b11 dlea>
#13000000
1b5gFK
0xUBRH
0Gp7Xm
b1 rz~),
b1 dlea>
#14000000
1Gp7Xm
b11 rz~),
b11 dlea>
#15000000
1xUBRH
0Gp7Xm
b10 rz~),
b10 dlea>
#16000000
1Gp7Xm
b11 rz~),
b11 dlea>
#17000000