fayalite

Add .to_trace_as_string() and clean up code

test.yml #389 -Commit cf3e6cfc6b pushed by programmerjake

master

2026-05-15 05:27:48 +00:00

4m46s

Add .to_trace_as_string() and clean up code

test.yml #388 -Commit cf3e6cfc6b pushed by programmerjake

#75

2026-05-15 05:17:51 +00:00

4m10s

add TraceAsString<T> -- sim traces it as a string rather than all its internal fields

test.yml #386 -Commit ea183eac87 pushed by programmerjake

master

2026-05-14 02:53:13 +00:00

4m54s

add TraceAsString<T> -- sim traces it as a string rather than all its internal fields

test.yml #385 -Commit ea183eac87 pushed by programmerjake

#74

2026-05-14 02:48:15 +00:00

4m16s

sim: properly update all VCD wires when they share simulation state

test.yml #382 -Commit 26224abe1c pushed by programmerjake

master

2026-05-06 04:27:05 +00:00

4m42s

sim: properly update all VCD wires when they share simulation state

test.yml #381 -Commit 26224abe1c pushed by programmerjake

#73

2026-05-06 04:22:19 +00:00

4m9s

redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue

test.yml #380 -Commit 2266315944 pushed by programmerjake

master

2026-05-04 06:38:15 +00:00

4m43s

redo #[hdl(sim)] match/let destructuring to support matching values of type Type::SimValue

test.yml #379 -Commit 2266315944 pushed by programmerjake

#72

2026-05-04 06:33:28 +00:00

7m18s

use #[hdl(cmp_eq)] for HdlOption and implement conversion <-> Option

test.yml #378 -Commit 7e9d7739fb pushed by programmerjake

master

2026-05-02 02:00:27 +00:00

4m41s

use #[hdl(cmp_eq)] for HdlOption and implement conversion <-> Option

test.yml #377 -Commit 7e9d7739fb pushed by programmerjake

#71

2026-05-02 01:55:40 +00:00

4m7s

add support for custom debug/display formatting of #[hdl] structs/enums

test.yml #376 -Commit 8e4eeef723 pushed by programmerjake

master

2026-05-01 06:23:14 +00:00

4m42s

add support for custom debug/display formatting of #[hdl] structs/enums

test.yml #375 -Commit 8e4eeef723 pushed by programmerjake

#70

2026-05-01 06:18:29 +00:00

4m7s

sim: Speed up updating traces by tracking which traces are written to

test.yml #374 -Commit 402f457c68 pushed by programmerjake

master

2026-05-01 02:23:30 +00:00

4m48s

sim: Speed up updating traces by tracking which traces are written to

test.yml #373 -Commit 402f457c68 pushed by programmerjake

#69

2026-05-01 02:18:37 +00:00

4m11s

change vcd output to have module contents under instance's name, more closely matching how it works in verilog

test.yml #370 -Commit 80b92c7dd3 pushed by programmerjake

master

2026-03-27 02:24:13 +00:00

4m55s

change vcd output to have module contents under instance's name, more closely matching how it works in verilog

test.yml #369 -Commit 80b92c7dd3 pushed by programmerjake

#68

2026-03-27 02:19:14 +00:00

4m18s

add simulator tests for queue()

test.yml #368 -Commit 2aa41137d4 pushed by programmerjake

master

2026-03-25 06:48:49 +00:00

5m3s

add simulator tests for queue()

test.yml #367 -Commit 2aa41137d4 pushed by programmerjake

#67

2026-03-25 06:43:42 +00:00

8m0s

update ui test's expected output for having rust-src available

test.yml #366 -Commit a93e66d8ab pushed by programmerjake

master

2026-03-18 03:59:45 +00:00

4m58s

update ui test's expected output for having rust-src available

test.yml #365 -Commit a93e66d8ab pushed by programmerjake

#66

2026-03-18 03:54:40 +00:00

4m21s

change VCD id generation to be based on hashing the path, making them better for git diff

test.yml #363 -Commit dbed947408 pushed by programmerjake

#65

2026-02-24 04:18:22 +00:00

7m50s

speed up simulation by optimizing SimulationImpl::read_traces

test.yml #360 -Commit c632e5d570 pushed by programmerjake

master

2026-02-04 23:52:35 +00:00

5m24s

speed up simulation by optimizing SimulationImpl::read_traces

test.yml #359 -Commit c632e5d570 pushed by programmerjake

#63

2026-02-04 23:46:27 +00:00

4m23s

speed up LazyInterned by redoing caching using RwLock and add a thread-local cache

test.yml #358 -Commit 1bc835803b pushed by programmerjake

master

2026-02-04 02:17:31 +00:00

5m33s

speed up LazyInterned by redoing caching using RwLock and add a thread-local cache

test.yml #357 -Commit 1bc835803b pushed by programmerjake

#62

2026-02-04 02:11:42 +00:00

4m28s

cache interned UInt/SInt types

test.yml #354 -Commit a96efa9696 pushed by programmerjake

master

2026-02-03 02:03:39 +00:00

4m44s

cache interned UInt/SInt types

test.yml #353 -Commit a96efa9696 pushed by programmerjake

#61

2026-02-03 01:58:50 +00:00

4m9s

don't compare function pointers -- they're non-deterministic

test.yml #352 -Commit e366793204 pushed by programmerjake

master

2026-01-12 11:24:36 +00:00

4m37s

don't compare function pointers -- they're non-deterministic

test.yml #351 -Commit e366793204 pushed by programmerjake

#60

2026-01-12 11:19:56 +00:00

4m6s

simplify SimValue Debug format, making complex structures much easier to read

test.yml #348 -Commit c97b44d9d6 pushed by programmerjake

master

2025-12-15 05:08:31 +00:00

4m31s