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sim: properly update all VCD wires when they share simulation state #73

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programmerjake merged 1 commit from programmerjake/fayalite:fix-sim-for-vcd-wires-sharing-sim-state into master 2026-05-06 04:22:21 +00:00
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programmerjake commented 2026-05-06 04:18:08 +00:00
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programmerjake added 1 commit 2026-05-06 04:18:08 +00:00
sim: properly update all VCD wires when they share simulation state
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programmerjake scheduled this pull request to auto merge when all checks succeed 2026-05-06 04:18:14 +00:00
programmerjake merged commit 26224abe1c into master 2026-05-06 04:22:21 +00:00
programmerjake deleted branch fix-sim-for-vcd-wires-sharing-sim-state 2026-05-06 04:22:21 +00:00
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Reference: libre-chip/fayalite#73
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Delete branch "programmerjake/fayalite:fix-sim-for-vcd-wires-sharing-sim-state"

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