reimplement fayalite::formal and add support to the simulator #77

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programmerjake merged 3 commits from programmerjake/fayalite:simulate-formal-inputs into master 2026-06-05 08:08:47 +00:00

Add support to the simulator for running hdl asserts/assumes and being
able to write to the formal global clock/reset and all any/all_const/seq that are used.
This allows you to use the exact same HDL code for running a simulation and for running a formal proof.

Add support to the simulator for running hdl asserts/assumes and being able to write to the formal global clock/reset and all `any/all_const/seq` that are used. This allows you to use the exact same HDL code for running a simulation and for running a formal proof.
programmerjake added 3 commits 2026-06-05 07:48:57 +00:00
Add support to the simulator for running hdl asserts/assumes and being
able to write to the formal global clock/reset and all any/all_const/seq that are used.
This allows you to use the exact same HDL code for running a simulation and for running a formal proof.
switch ready_valid::queue formal proofs to use formal_global_clock
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/ test (pull_request) Failing after 3m9s
e7ee1e862e
programmerjake force-pushed simulate-formal-inputs from e7ee1e862e to ffca1a279d 2026-06-05 07:57:22 +00:00 Compare
programmerjake merged commit ffca1a279d into master 2026-06-05 08:08:47 +00:00
programmerjake deleted branch simulate-formal-inputs 2026-06-05 08:08:47 +00:00
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Reference: libre-chip/fayalite#77
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