Add more caching, reduce the number of duplicate wires in generated FIRRTL, and make Module verification check that expressions are visible #76

Merged

programmerjake merged 4 commits from programmerjake/fayalite:optimize-more into master 2026-06-02 08:31:37 +00:00

Conversation 0 Commits 4 Files changed 5 +996 -627

programmerjake commented 2026-06-02 08:26:05 +00:00

Owner

Copy link

These help catch bugs and help speed up the formal proofs in libre-chip/cpu#15

These help catch bugs and help speed up the formal proofs in https://git.libre-chip.org/libre-chip/cpu/pulls/15

programmerjake added 4 commits 2026-06-02 08:26:06 +00:00

speed up TraceAsString by caching the canonical type for can_substitute_type 1880ed682f

firrtl: don't generate as many duplicate wires when compiling expressions 6902aea3a6

simplify_enums: cache folded expressions b1116c4a1a

fayalite/src/module: check that expressions are visible where they are used, e.g. erroring when a wire is inside an if but used outside. 31353862ce

programmerjake merged commit 31353862ce into master 2026-06-02 08:31:37 +00:00

programmerjake deleted branch optimize-more 2026-06-02 08:31:37 +00:00

Sign in to join this conversation.

Reviewers

No reviewers

Labels

Clear labels

No items

No labels

Milestone

Clear milestone

No items

No milestone

Projects

Clear projects

No items

No project

Assignees

Clear assignees

No assignees

1 participant

Notifications

Subscribe

Due date

The due date is invalid or out of range. Please use the format "yyyy-mm-dd".

No due date set.

Dependencies

No dependencies set.

Reference: libre-chip/fayalite#76

No description provided.