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fayalite::build::verilog: tell firtool to only preserve values with significant names #79

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programmerjake merged 1 commit from programmerjake/fayalite:firtool-preserve-only-significant-names into master 2026-06-15 01:54:48 +00:00
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programmerjake commented 2026-06-15 01:49:57 +00:00
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this makes test_power_isa_add_formal take ~2.5min instead of 7-9min it was taking

this makes `test_power_isa_add_formal` take ~2.5min instead of 7-9min it was taking
programmerjake added 1 commit 2026-06-15 01:49:58 +00:00
fayalite::build::verilog: tell firtool to only preserve values with significant names
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programmerjake scheduled this pull request to auto merge when all checks succeed 2026-06-15 01:50:03 +00:00
programmerjake merged commit bb34aeb7f1 into master 2026-06-15 01:54:48 +00:00
programmerjake deleted branch firtool-preserve-only-significant-names 2026-06-15 01:54:49 +00:00
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Reference: libre-chip/fayalite#79
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Delete branch "programmerjake/fayalite:firtool-preserve-only-significant-names"

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