libre-chip/fayalite
3
0
Fork 3
Code Issues 1 Pull requests Projects Releases Packages Wiki Activity Actions

fayalite::build::verilog: tell firtool to only preserve values with significant names
All checks were successful
/ test (pull_request) Successful in 4m46s
Details
/ test (push) Successful in 5m17s
Details

Browse source
This commit is contained in:
Jacob Lifshay 2026-06-14 18:46:06 -07:00
parent 7ddb4780fa
commit bb34aeb7f1
Signed by: programmerjake
SSH key fingerprint: SHA256:HnFTLGpSm4Q4Fj502oCFisjZSoakwEuTsJJMSke63RQ
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
crates/fayalite/src/build/verilog.rs
View file

@ -211,7 +211,7 @@ impl ExternalCommand for UnadjustedVerilog {
args.write_arg("-o");
args.write_interned_arg(unadjusted_verilog_file_name);
if verilog_debug {
args.write_args(["-g", "--preserve-values=all"]);
args.write_args(["-g", "--preserve-values=named"]);
}
if let Some(dialect) = verilog_dialect {
args.write_args(dialect.firtool_extra_args().iter().copied());