Akash Levy
a67471d7f9
Merge pull request #115 from Silimate/sat_clkgate
...
Sat clkgate
2026-03-04 18:02:27 -08:00
AdvaySingh1
e2b71b0d55
Added -word arg
2026-03-04 14:51:47 -08:00
abhinavputhran
94c789e9c8
setundef: respect selection for cells, processes, and connections
...
Previously, setundef would rewrite sigspecs in all cells, processes,
and connections regardless of the active selection. Only modules and
memories were correctly filtered by selection.
Fix by using module->selected_cells() for cells, adding a
module->selected() check for processes, and checking wire selection
on the lhs of each connection before rewriting.
Fixes #5624
2026-03-04 17:48:35 -05:00
AdvaySingh1
26adc17fd7
Revert "Changed to for chacterization"
...
Removing changing _DFF_ to dff for chacterization
2026-03-04 10:43:53 -08:00
Emil J
0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes
...
celltypes: compile-time lookup tables for internal cells
2026-03-04 14:47:57 +00:00
nella
66bd4716cf
rtlil use newcelltypes.
2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
ecb8b20f62
yosys: use newcelltypes for yosys_celltypes users
2026-03-04 12:39:44 +01:00
Emil J. Tywoniak
4ab22cbb97
abc: use newcelltypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
07ec8708e4
share: use newcelltypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
9e59f05c25
newcelltypes: wrap design celltypes support
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
35ccaa60d7
newcelltypes: TurboCellTypes -> StaticCellTypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
6adc08b0e5
opt_expr: use newcelltypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
3671d577a0
opt_clean: use newcelltypes
2026-03-04 12:22:14 +01:00
Miodrag Milanović
05d1d56b9d
Merge pull request #5704 from apullin/apullin/abc9-no-loops-fix
...
abc9: preserve topological-loop asserts with targeted SCC fallback
2026-03-04 11:09:38 +01:00
Miodrag Milanovic
b7d013e6bf
Fix help message for equiv passes
2026-03-04 07:46:40 +01:00
Akash Levy
d05236907a
Merge branch 'main' into sim
2026-03-03 20:58:07 -08:00
Akash Levy
96104b4431
Merge branch 'main' into sat_clkgate
2026-03-03 20:57:42 -08:00
Akash Levy
958f1c608a
Merge pull request #116 from Silimate/autoscope
...
Autoscope
2026-03-03 20:49:13 -08:00
Tianji Liu
750d536bba
abc: new option to pass ABC read_lib args
2026-03-04 11:24:24 +08:00
Emil J. Tywoniak
6f74c54c02
async2sync: $dffsr has undef output on S&R
2026-03-03 10:34:29 +01:00
Emil J. Tywoniak
a53104379d
clk2fflogic: $dffsr has undef output on S&R
2026-03-03 10:34:29 +01:00
tondapusili
b438fd1fe9
negopt: fix quadratic blowup by adding index hints and deferring nusers to filter
2026-03-02 19:33:25 -08:00
Stan Lee
da25b800bc
finalized
2026-03-02 11:05:44 -08:00
Akash Levy
7d96a7f73c
Update aigmap to go a lot faster using aig template cache and uniquify cache
2026-03-01 22:35:06 -08:00
Akash Levy
b03f73653f
Update abc to fix bug
2026-03-01 21:43:26 -08:00
Stan Lee
c459a74c13
autoscoping
2026-03-01 15:39:35 -08:00
KrystalDelusion
1d3f9b7905
Merge pull request #5687 from YosysHQ/nella/pdr-doc
...
Update help text for rename -witness and write_aiger -ywmap
2026-03-02 09:29:25 +13:00
Akash Levy
7a35a982d3
Merge pull request #111 from Silimate/timing_balance_impl
...
silimate: add opt_timing_balance pass and tests
2026-02-28 12:22:23 -08:00
AdvaySingh1
877e97de06
Changed to for chacterization
2026-02-27 15:23:50 -08:00
Advay Singh
8974f3473f
Update passes/silimate/infer_ce.cc
...
Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
2026-02-27 12:37:49 -08:00
AdvaySingh1
90aa1cc016
Checked out main passes/techmap/clockgate.cc for source attributes and removed logging
2026-02-27 12:24:31 -08:00
AdvaySingh1
3cee420bf9
Merge branch 'main' into sat_clkgate
2026-02-27 11:15:22 -08:00
tondapusili
f46b8d2a44
silimate: add opt_timing_balance pass and tests
2026-02-27 09:13:39 -08:00
Andrew Pullin
5970be33fb
abc9: preserve topological-loop asserts with targeted SCC fallback
...
A real-world ABC9 flow hit residual combinational loops after SCC breaking, tripping the prep_xaiger loop assertion.
Keep the existing topological assertions in place (prep_xaiger and reintegrate still assert no_loops).
To handle residual non-box loops, add a targeted fallback in prep_xaiger: when loops remain after normal SCC breaking, insert additional $__ABC9_SCC_BREAKER cuts on non-box loop cells, rebuild toposort, and then re-check the existing assertion.
Also keep pre-ABC9 SCC tagging on all cell types (scc -all_cell_types) and add a regression test (tests/techmap/abc9-nonbox-loop-with-box.ys).
2026-02-26 22:30:32 -08:00
Stan Lee
29a1c69f74
move log flush to better spot
2026-02-26 16:01:37 -08:00
Stan Lee
b11eef4fe1
fix bug
2026-02-26 16:00:27 -08:00
tondapusili
2f276d0723
Added log flushes after each negopt pass for clearer logging
2026-02-25 12:15:46 -08:00
Emil J
5f8489d36d
Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors
...
equiv_induct: error on missing model
2026-02-25 15:39:31 +01:00
Akash Levy
0b46d8b201
Merge pull request #109 from Silimate/clkgate_attr
...
Added is_clock_gated attr to flops created via clockgate.cc pass
2026-02-20 17:02:02 -08:00
AdvaySingh1
ec537b189f
Added is_clock_gated attr to flops created via clockgate.cc pass
2026-02-20 11:34:50 -08:00
AdvaySingh1
8f5b8cb46c
Added is_clock_gated attr to flops created via clockgate.cc pass
2026-02-20 11:34:08 -08:00
Miodrag Milanović
0ed7c5ad53
Merge pull request #5620 from YosysHQ/lofty/abc9-verify
...
abc9: verify post-mapping equivalence by default
2026-02-20 13:41:11 +01:00
Krystine Sherwin
094481739f
memory_libmap: Add -force-params
...
Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
2026-02-20 10:57:00 +00:00
AdvaySingh1
84a03a6b9a
Merge branch 'icg_builtin_sim' into sat_clkgate
2026-02-19 11:51:49 -08:00
AdvaySingh1
b29514fafc
Added built in cell alongside sim support for cell
2026-02-19 11:48:35 -08:00
AdvaySingh1
d9867fc7c7
Merge branch 'main' into sat_clkgate
2026-02-19 09:43:22 -08:00
AdvaySingh1
5e58bf22e0
Changed param naming for consistancy
2026-02-19 09:42:59 -08:00
Akash Levy
723ddd74cf
Improve wreduce runtime
2026-02-19 01:03:26 -08:00
AdvaySingh1
5769cdbea8
Added node retention
2026-02-18 16:05:56 -08:00
AdvaySingh1
d84e56ecac
Added naming for the new icg cells
2026-02-18 16:03:34 -08:00
