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yosys/passes
abhinavputhran 94c789e9c8 setundef: respect selection for cells, processes, and connections
Previously, setundef would rewrite sigspecs in all cells, processes,
and connections regardless of the active selection. Only modules and
memories were correctly filtered by selection.

Fix by using module->selected_cells() for cells, adding a
module->selected() check for processes, and checking wire selection
on the lhs of each connection before rewriting.

Fixes #5624
2026-03-04 17:48:35 -05:00
..
cmds setundef: respect selection for cells, processes, and connections 2026-03-04 17:48:35 -05:00
equiv Merge pull request #5512 from YosysHQ/emil/turbo-celltypes 2026-03-04 14:47:57 +00:00
fsm fsm_detect: add adff detection 2025-11-06 23:29:47 +02:00
hierarchy hierarchy.cc: Tidying 2025-10-15 09:42:47 +13:00
memory memory_libmap: Add -force-params 2026-02-20 10:57:00 +00:00
opt share: use newcelltypes 2026-03-04 12:22:14 +01:00
pmgen Remove .c_str() from log_cmd_error() and log_file_error() parameters 2025-09-16 22:59:08 +00:00
proc proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
sat yosys: use newcelltypes for yosys_celltypes users 2026-03-04 12:39:44 +01:00
techmap Merge pull request #5512 from YosysHQ/emil/turbo-celltypes 2026-03-04 14:47:57 +00:00
tests test_cell.cc: Generate .aag for all compatible cells 2025-12-02 14:03:36 +13:00