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yosys/passes
2026-03-01 15:39:35 -08:00
..
cmds Merge from main 2026-02-13 04:14:08 -08:00
equiv
fsm
hierarchy
memory Fix cell naming issues 2026-02-13 01:05:51 -08:00
opt Improve wreduce runtime 2026-02-19 01:03:26 -08:00
pmgen
proc proc_clean: Removing an empty full_case is doing something 2026-01-07 13:10:32 +13:00
sat autoscoping 2026-03-01 15:39:35 -08:00
silimate autoscoping 2026-03-01 15:39:35 -08:00
techmap Added is_clock_gated attr to flops created via clockgate.cc pass 2026-02-20 11:34:08 -08:00
tests test_cell.cc: Generate .aag for all compatible cells 2025-12-02 14:03:36 +13:00