5823 commits

Author	SHA1	Message	Date
nella	46df888191	impl csa tree.	2026-04-13 12:48:05 +02:00
Lofty	564c617721	Merge pull request #5790 from Eiko-Eira/main ... Fixed typos and incorrect grammar	2026-04-11 03:26:55 +00:00
AdvaySingh1	cf78adc729	Made file opening more safe	2026-04-10 13:10:51 -07:00
Advay Singh	03554f0d58	Update passes/silimate/report_fanout.cc ... Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>	2026-04-10 13:01:26 -07:00
Advay Singh	f8ea10d50c	Update passes/silimate/report_fanout.cc ... Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>	2026-04-10 13:01:07 -07:00
AdvaySingh1	54bcc49987	ENG-1872	2026-04-10 12:54:43 -07:00
Akash Levy	485cc675e5	Merge pull request #144 from Silimate/sim ... [ENG-1869] Normalize scopes	2026-04-09 19:11:11 -07:00
Akash Levy	300c64773b	Fix offset in splitcells	2026-04-09 16:20:26 -07:00
Stan Lee	0bf20fdd19	handle edge cases	2026-04-08 16:33:10 -07:00
Stan Lee	146491af22	normalize scope	2026-04-08 16:18:55 -07:00
Emil J	86448c0001	Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef ... Undefine set&reset behavior of $dffsr	2026-04-08 14:22:34 +00:00
Akash Levy	ed11f4c135	Fix crash due to lack of A/Y ports	2026-04-08 00:28:43 -07:00
Akash Levy	6daa8a01ed	opt_vps improvements for VPS read	2026-04-07 22:07:14 -07:00
Emil J. Tywoniak	41b69df2cb	abc_new: stable TopoSort	2026-04-06 15:09:52 +02:00
AdvaySingh1	30950ee599	Fixed P1 issues	2026-04-03 17:00:56 -07:00
AdvaySingh1	b103fdb047	Updated the cone_partition	2026-04-03 16:31:02 -07:00
AdvaySingh1	9b98fec18a	Renamed FFs	2026-04-03 14:30:24 -07:00
Akash Levy	1820526a9a	opt_vps	2026-04-03 01:15:17 -07:00
Akash Levy	768f2aa00b	Merge pull request #139 from Silimate/sim ... Add log-interval	2026-04-02 15:24:24 -07:00
Stan Lee	f46ce5179f	greptile	2026-04-02 11:15:39 -07:00
Stan Lee	8bdbe82819	add log-interval	2026-04-02 10:12:39 -07:00
Noah Van Dijk	52243e10fb	Fix typo in pmgen/README.md ... Line 161: calulated > calculated	2026-04-02 10:24:31 -05:00
Akash Levy	5082625d71	opt_shift	2026-04-02 00:43:06 -07:00
Akash Levy	72db8885aa	Merge pull request #137 from Silimate/sim ... Support for N-dimensional arrays in simulation	2026-04-01 11:00:49 -07:00
Stan Lee	91345c2283	warning msg and address spaces	2026-04-01 09:21:02 -07:00
Stan Lee	286303deca	Compilation fix	2026-03-31 12:57:27 -07:00
Stan Lee	b6f118091c	Support for N-dimensional arrays in simulation	2026-03-31 12:50:36 -07:00
AdvaySingh1	60d5e40897	Merge branch 'main' into remove_filter_non_trigger_outputs	2026-03-31 10:13:06 -07:00
AdvaySingh1	aea16d3888	Removed -filter_non_trigger_outputs functionality	2026-03-31 10:12:21 -07:00
Emil J	cede13a742	Merge pull request #5765 from YosysHQ/emil/muxpack-wide-port ... muxpack: fix wide Y port handling	2026-03-31 10:49:39 +00:00
Akash Levy	b2e7c10bb7	Merge pull request #134 from Silimate/negopt_runtime_fix ... [ENG-1692] negopt runtime fix + small cleanup	2026-03-30 17:32:13 -07:00
Akash Levy	db1e0701b0	Apply suggestions from code review ... Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>	2026-03-30 17:31:59 -07:00
Stan Lee	87e959d14c	add warning message	2026-03-30 16:34:20 -07:00
Abhinav Tondapu	df43a3097a	[ENG-1692] negopt runtime fix + small cleanup	2026-03-30 16:30:46 -07:00
Akash Levy	5e7e172570	Merge pull request #133 from Silimate/sim ... Better support for arrays in RTL + VCD	2026-03-30 15:12:11 -07:00
Stan Lee	c767d90f3d	add warning	2026-03-30 14:13:43 -07:00
Stan Lee	e10f545c69	fixes	2026-03-30 13:13:14 -07:00
Stan Lee	857f356f1f	remove ambiguity in implementation	2026-03-30 12:26:44 -07:00
Stan Lee	01f0fd751f	fixes for arrays	2026-03-30 12:13:50 -07:00
AdvaySingh1	8aebec79a8	Added -filter_non_trigger_outputs knob	2026-03-27 15:41:44 -07:00
AdvaySingh1	ad6546b05e	Revert "Update passes/techmap/abc.cc" ... This reverts commit 20cf9fb461.	2026-03-27 14:53:38 -07:00
Advay Singh	20cf9fb461	Update passes/techmap/abc.cc ... Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>	2026-03-27 12:45:57 -07:00
AdvaySingh1	113b3e02ce	Removed adding struct partition object file	2026-03-26 16:59:58 -07:00
AdvaySingh1	972e4780c9	Removed extra struct partition pass	2026-03-26 16:58:09 -07:00
AdvaySingh1	f523760b75	merged with main	2026-03-26 16:50:59 -07:00
AdvaySingh1	f42a63941c	Added initial clkmerge pass for multiple clock domains	2026-03-26 16:42:27 -07:00
Abhinav Tondapu	510ef01b09	adding temp debug logs to fix runtime issue	2026-03-25 16:55:29 -07:00
AdvaySingh1	92e659f42a	Added new port outputs anding the clock domain. TODO: fix if they belong to the same one and there's multiple	2026-03-24 20:00:24 -07:00
tondapusili	5b22e64d19	sim: cache sigmap in register_output_step_values	2026-03-24 16:10:11 -07:00
AdvaySingh1	f7a9af5252	Make the signal_map flag optional	2026-03-24 14:39:21 -07:00