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autoscoping

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This commit is contained in:
Stan Lee 2026-03-01 15:39:35 -08:00
parent 0b46d8b201
commit c459a74c13
4 changed files with 114 additions and 8 deletions
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18
passes/sat/sim.cc
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@ -1474,8 +1474,22 @@ struct SimWorker : SimShared
log_assert(top == nullptr);
fst = new FstData(sim_filename);
timescale = fst->getTimescaleString();
if (scope.empty())
log_error("Scope must be defined for co-simulation.\n");
if (scope.empty()) {
scope = fst->autoScope(topmod);
if (scope.empty()) {
std::set<std::string> unique_scopes;
for (const auto& var : fst->getVars()) {
unique_scopes.insert(var.scope);
}
log_warning("Available scopes:\n");
for (const auto& scope : unique_scopes) {
log_warning(" %s\n", scope.c_str());
}
log_error("No scope found for module '%s'. Please specify -scope explicitly with above options.\n",
RTLIL::unescape_id(topmod->name).c_str());
}
}
log("Using scope: \"%s\"\n", scope.c_str());
top = new SimInstance(this, scope, topmod);
register_signals();

29
passes/silimate/reg_rename.cc
View file

@ -188,15 +188,35 @@ struct RegRenamePass : public Pass {
}
extra_args(args, argidx, design);
// Extract top module
Module *topmod = design->top_module();
if (!topmod)
log_error("No top module found!\n");
// Extract pre-optimization register widths from VCD file
dict<std::pair<std::string, std::string>, int> vcd_reg_widths;
if (!vcd_filename.empty()) {
if (scope.empty()) {
log_error("No scope provided. Use -scope option.\n");
}
log("Reading VCD file: %s\n", vcd_filename.c_str());
try {
FstData fst(vcd_filename);
if (scope.empty()) {
scope = fst.autoScope(topmod);
if (scope.empty()) {
log_warning("No scope found for module '%s'. Please specify -scope explicitly.\n",
RTLIL::unescape_id(topmod->name).c_str());
std::set<std::string> unique_scopes;
for (const auto& var : fst.getVars()) {
unique_scopes.insert(var.scope);
}
log_warning("Available scopes:\n");
for (const auto& scope : unique_scopes) {
log_warning(" %s\n", scope.c_str());
}
log_error("No scope found for module '%s'. Please specify -scope explicitly with above options.\n",
RTLIL::unescape_id(topmod->name).c_str());
}
}
log("Using scope: \"%s\"\n", scope.c_str());
for (auto &var : fst.getVars()) {
if (var.is_reg) {
std::string reg_vcd_scope = var.scope;
@ -223,9 +243,6 @@ struct RegRenamePass : public Pass {
}
// STEP 2: Build hierarchy and process
Module *topmod = design->top_module();
if (!topmod)
log_error("No top module found!\n");
log("Building hierarchy from scope: %s\n", scope.c_str());
// Build hierarchy and process register renamings