mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-15 11:45:41 +00:00
Code Activity

Merge pull request #139 from Silimate/sim

Browse source 
Add log-interval
This commit is contained in:
Akash Levy 2026-04-02 15:24:24 -07:00 • committed by GitHub
commit 768f2aa00b
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
1 changed files with 33 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

37
passes/sat/sim.cc
View file

@ -1538,7 +1538,7 @@ struct SimWorker : SimShared
write_output_files();
}
void run_cosim_fst(Module *topmod, int numcycles)
void run_cosim_fst(Module *topmod, int numcycles, int log_interval)
{
log_assert(top == nullptr);
fst = new FstData(sim_filename);
@ -1641,6 +1641,7 @@ struct SimWorker : SimShared
bool initial = true;
int cycle = 0;
uint64_t last_time = startCount;
log("Co-simulation from %lu%s to %lu%s", (unsigned long)startCount, fst->getTimescaleString(), (unsigned long)stopCount, fst->getTimescaleString());
if (cycles_set)
log(" for %d clock cycle(s)",numcycles);
@ -1649,8 +1650,22 @@ struct SimWorker : SimShared
unsigned int end_cycle = cycles_set ? numcycles*2 : INT_MAX;
fst->reconstructAllAtTimes(fst_clock, startCount, stopCount, end_cycle, [&](uint64_t time) {
// Log progress every log_interval
if (log_interval > 0 && cycle > 0 && cycle % log_interval == 0) {
log("Completed %d %s at %lu%s\n",
cycle,
(all_samples ? "samples" : "cycles"),
(unsigned long)time,
fst->getTimescaleString());
}
if (verbose)
log("Co-simulating %s %d [%lu%s].\n", (all_samples ? "sample" : "cycle"), cycle, (unsigned long)time, fst->getTimescaleString());
log("Co-simulating %s %d [%lu%s].\n",
(all_samples ? "sample" : "cycle"),
cycle,
(unsigned long)time,
fst->getTimescaleString());
bool did_something = top->setInputs();
if (initial) {
@ -1661,6 +1676,7 @@ struct SimWorker : SimShared
if (did_something)
update(true);
register_output_step(time);
last_time = time;
bool status = top->checkSignals();
if (status)
@ -1668,6 +1684,12 @@ struct SimWorker : SimShared
cycle++;
});
log("Co-simulation complete: %d %s at %lu%s\n",
cycle,
(all_samples ? "samples" : "cycles"),
(unsigned long)last_time,
fst->getTimescaleString());
write_output_files();
delete fst;
}
@ -3008,6 +3030,9 @@ struct SimPass : public Pass {
log(" -d\n");
log(" enable debug output\n");
log("\n");
log(" -log-interval <integer>\n");
log(" log progress every N cycles (if clock is specified) or samples (otherwise). Defaults to 0 (no logging)\n");
log("\n");
}
@ -3021,7 +3046,7 @@ struct SimPass : public Pass {
SimWorker worker;
int numcycles = 20;
int cycle_width = 10;
int append = 0;
int append = 0, log_interval = 0;
bool start_set = false, stop_set = false, at_set = false;
log_header(design, "Executing SIM pass (simulate the circuit).\n");
@ -3095,6 +3120,10 @@ struct SimPass : public Pass {
worker.debug = true;
continue;
}
if (args[argidx] == "-log-interval" && argidx+1 < args.size()) {
log_interval = atoi(args[++argidx].c_str());
continue;
}
if (args[argidx] == "-w") {
worker.writeback = true;
continue;
@ -3219,7 +3248,7 @@ struct SimPass : public Pass {
std::string filename_trim = file_base_name(worker.sim_filename);
if (filename_trim.size() > 4 && ((filename_trim.compare(filename_trim.size()-4, std::string::npos, ".fst") == 0) ||
filename_trim.compare(filename_trim.size()-4, std::string::npos, ".vcd") == 0)) {
worker.run_cosim_fst(top_mod, numcycles);
worker.run_cosim_fst(top_mod, numcycles, log_interval);
} else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".aiw") == 0) {
if (worker.map_filename.empty())
log_cmd_error("For AIGER witness file map parameter is mandatory.\n");