1682 commits

Author	SHA1	Message	Date
William Speirs	31267a1ae8	Header changes so it will compile on VS	2014-10-17 11:41:36 +02:00
William Speirs	fda52f05f2	Wrapped math in int constructor	2014-10-17 11:28:14 +02:00
Clifford Wolf	3838856a9e	Print "SystemVerilog" in "read_verilog -sv" log messages	2014-10-16 10:31:54 +02:00
Clifford Wolf	6b05a9e807	Fixed handling of invalid array access in mem2reg code	2014-10-16 00:44:23 +02:00
Clifford Wolf	f65e1c309f	Updated .gitignore file for ilang and verilog frontends	2014-10-15 01:14:38 +02:00
Clifford Wolf	c3e9922b5d	Replaced readsome() with read() and gcount()	2014-10-15 01:12:53 +02:00
William Speirs	fad0b0c506	Updated lexers & parsers to include prefixes	2014-10-15 00:48:19 +02:00
Clifford Wolf	0b9282a779	Added make_temp_{file,dir}() and remove_directory() APIs	2014-10-12 12:11:57 +02:00
Clifford Wolf	b1596bc0e7	Added run_command() api to replace system() and popen()	2014-10-12 10:57:15 +02:00
Clifford Wolf	35fbc0b35f	Do not the 'z' modifier in format string (another win32 fix)	2014-10-11 11:42:08 +02:00
Clifford Wolf	8263f6a74a	Fixed win32 troubles with f.readsome()	2014-10-11 11:36:22 +02:00
Clifford Wolf	0a651f112f	Disabled vhdl2verilog command for win32 builds	2014-10-11 10:46:19 +02:00
Clifford Wolf	bbd808072b	Added format __attribute__ to stringf()	2014-10-10 17:22:08 +02:00
Clifford Wolf	4569a747f8	Renamed SIZE() to GetSize() because of name collision on Win32	2014-10-10 17:07:24 +02:00
Clifford Wolf	f9a307a50b	namespace Yosys	2014-09-27 16:17:53 +02:00
Clifford Wolf	48b00dccea	Another $clog2 bugfix	2014-09-08 12:25:23 +02:00
Clifford Wolf	680eaaac41	Fixed $clog2 (off by one error)	2014-09-06 19:31:04 +02:00
Clifford Wolf	deff416ea7	Fixed assignment of out-of bounds array element	2014-09-06 17:58:27 +02:00
Ruben Undheim	79cbf9067c	Corrected spelling mistakes found by lintian	2014-09-06 08:47:06 +02:00
Clifford Wolf	8927aa6148	Removed $bu0 cell type	2014-09-04 02:07:52 +02:00
Clifford Wolf	58367cd87a	Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore	2014-08-23 15:14:58 +02:00
Clifford Wolf	19cff41eb4	Changed frontend-api from FILE to std::istream	2014-08-23 15:03:55 +02:00
Clifford Wolf	98442e019d	Added emscripten (emcc) support to build system and some build fixes	2014-08-22 16:20:22 +02:00
Clifford Wolf	e218f0eacf	Added support for non-standard <plugin>:<c_name> DPI syntax	2014-08-22 14:30:29 +02:00
Clifford Wolf	74af3a2b70	Archibald Rust and Clifford Wolf: ffi-based dpi_call()	2014-08-22 14:22:09 +02:00
Clifford Wolf	ad146c2582	Fixed small memory leak in ast simplify	2014-08-21 17:33:40 +02:00
Clifford Wolf	6c5cafcd8b	Added support for DPI function with different names in C and Verilog	2014-08-21 17:22:04 +02:00
Clifford Wolf	085c8e873d	Added AstNode::asInt()	2014-08-21 17:11:51 +02:00
Clifford Wolf	490d7a5bf2	Fixed memory leak in DPI function calls	2014-08-21 13:09:47 +02:00
Clifford Wolf	7bfc4ae120	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	2014-08-21 12:43:51 +02:00
Clifford Wolf	38addd4c67	Added support for global tasks and functions	2014-08-21 12:42:28 +02:00
Clifford Wolf	640d9fc551	Added "via_celltype" attribute on task/func	2014-08-18 14:29:30 +02:00
Clifford Wolf	acb435b6cf	Added const folding of AST_CASE to AST simplifier	2014-08-18 00:02:30 +02:00
Clifford Wolf	64713647a9	Improved AST ProcessGenerator performance	2014-08-17 02:17:49 +02:00
Clifford Wolf	d491fd8c19	Use stackmap<> in AST ProcessGenerator	2014-08-17 00:57:24 +02:00
Clifford Wolf	7f734ecc09	Added module->uniquify()	2014-08-16 23:50:36 +02:00
Clifford Wolf	83e2698e10	AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map	2014-08-16 19:31:59 +02:00
Clifford Wolf	f092b50148	Renamed $_INV_ cell type to $_NOT_	2014-08-15 14:11:40 +02:00
Clifford Wolf	c7afbd9d8e	Fixed bug in "read_verilog -ignore_redef"	2014-08-15 01:53:22 +02:00
Clifford Wolf	978a933b6a	Added RTLIL::SigSpec::to_sigbit_map()	2014-08-14 23:14:47 +02:00
Clifford Wolf	c83b990458	Changed the AST genWidthRTLIL subst interface to use a std::map	2014-08-14 23:02:07 +02:00
Clifford Wolf	6d56172c0d	Fixed line numbers when using here-doc macros	2014-08-14 22:26:30 +02:00
Clifford Wolf	85e3cc12ac	Fixed handling of task outputs	2014-08-14 22:26:10 +02:00
Clifford Wolf	1bf7a18fec	Added module->ports	2014-08-14 16:22:52 +02:00
Clifford Wolf	f53984795d	Added support for non-standard """ macro bodies	2014-08-13 13:03:38 +02:00
Clifford Wolf	593264e9ed	Fixed building verific bindings	2014-08-12 15:21:06 +02:00
Clifford Wolf	2dc3333734	Also allow "module foobar(input foo, output bar, ...);" syntax	2014-08-07 16:41:27 +02:00
Clifford Wolf	d259abbda2	Added AST_MULTIRANGE (arrays with more than 1 dimension)	2014-08-06 15:52:54 +02:00
Clifford Wolf	91dd87e60b	Improved scope resolution of local regs in Verilog+AST frontend	2014-08-05 12:15:53 +02:00
Clifford Wolf	0129d41efa	Fixed AST handling of variables declared inside a functions main block	2014-08-05 08:35:51 +02:00