mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-27 02:45:52 +00:00
Code Activity

Renamed SIZE() to GetSize() because of name collision on Win32

Browse source
This commit is contained in:
Clifford Wolf 2014-10-10 16:59:44 +02:00
parent c7f5aab625
commit 4569a747f8
48 changed files with 447 additions and 447 deletions
Download patch file Download diff file Expand all files Collapse all files

4
frontends/ast/dpicall.cc
View file

@ -75,8 +75,8 @@ AST::AstNode *AST::dpi_call(const std::string &rtype, const std::string &fname,
log("Calling DPI function `%s' and returning `%s':\n", fname.c_str(), rtype.c_str());
log_assert(SIZE(args) == SIZE(argtypes));
for (int i = 0; i < SIZE(args); i++) {
log_assert(GetSize(args) == GetSize(argtypes));
for (int i = 0; i < GetSize(args); i++) {
if (argtypes[i] == "real") {
log(" arg %d (%s): %f\n", i, argtypes[i].c_str(), args[i]->asReal(args[i]->is_signed));
value_store[i].f64 = args[i]->asReal(args[i]->is_signed);

16
frontends/ast/genrtlil.cc
View file

@ -254,7 +254,7 @@ struct AST_INTERNAL::ProcessGenerator
// create initial assignments for the temporary signals
if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) {
subst_rvalue_map = subst_lvalue_from.to_sigbit_map(RTLIL::SigSpec(RTLIL::State::Sx, SIZE(subst_lvalue_from)));
subst_rvalue_map = subst_lvalue_from.to_sigbit_map(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from)));
} else {
addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
}
@ -289,8 +289,8 @@ struct AST_INTERNAL::ProcessGenerator
{
RTLIL::SigSpec new_lhs, new_rhs;
log_assert(SIZE(lhs) == SIZE(rhs));
for (int i = 0; i < SIZE(lhs); i++) {
log_assert(GetSize(lhs) == GetSize(rhs));
for (int i = 0; i < GetSize(lhs); i++) {
if (lhs[i].wire == nullptr)
continue;
new_lhs.append(lhs[i]);
@ -306,7 +306,7 @@ struct AST_INTERNAL::ProcessGenerator
{
std::vector<RTLIL::SigChunk> chunks = sig.chunks();
for (int i = 0; i < SIZE(chunks); i++)
for (int i = 0; i < GetSize(chunks); i++)
{
RTLIL::SigChunk &chunk = chunks[i];
if (chunk.wire == NULL)
@ -430,7 +430,7 @@ struct AST_INTERNAL::ProcessGenerator
lvalue.replace(subst_lvalue_map.stdmap());
if (ast->type == AST_ASSIGN_EQ) {
for (int i = 0; i < SIZE(unmapped_lvalue); i++)
for (int i = 0; i < GetSize(unmapped_lvalue); i++)
subst_rvalue_map.set(unmapped_lvalue[i], rvalue[i]);
}
@ -472,7 +472,7 @@ struct AST_INTERNAL::ProcessGenerator
subst_lvalue_map.save();
subst_rvalue_map.save();
for (int i = 0; i < SIZE(this_case_eq_lvalue); i++)
for (int i = 0; i < GetSize(this_case_eq_lvalue); i++)
subst_lvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
RTLIL::CaseRule *backup_case = current_case;
@ -507,7 +507,7 @@ struct AST_INTERNAL::ProcessGenerator
sw->cases.push_back(default_case);
}
for (int i = 0; i < SIZE(this_case_eq_lvalue); i++)
for (int i = 0; i < GetSize(this_case_eq_lvalue); i++)
subst_rvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
this_case_eq_lvalue.replace(subst_lvalue_map.stdmap());
@ -941,7 +941,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast->children[1]->is_signed);
fake_ast->children[1]->is_signed = true;
}
if (SIZE(shift_val) >= 32)
if (GetSize(shift_val) >= 32)
fake_ast->children[1]->is_signed = true;
RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shiftx", width, fake_ast->children[0]->genRTLIL(), shift_val);
delete left_at_zero_ast;

20
frontends/ast/simplify.cc
View file

@ -575,9 +575,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
{
AstNode *index_expr = nullptr;
for (int i = 0; 2*i < SIZE(id2ast->multirange_dimensions); i++)
for (int i = 0; 2*i < GetSize(id2ast->multirange_dimensions); i++)
{
if (SIZE(children[0]->children) < i)
if (GetSize(children[0]->children) < i)
log_error("Insufficient number of array indices for %s at %s:%d.\n", log_id(str), filename.c_str(), linenum);
AstNode *new_index_expr = children[0]->children[i]->children.at(0)->clone();
@ -591,7 +591,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
index_expr = new AstNode(AST_ADD, new AstNode(AST_MUL, index_expr, AstNode::mkconst_int(id2ast->multirange_dimensions[2*i-1], true)), new_index_expr);
}
for (int i = SIZE(id2ast->multirange_dimensions)/1; i < SIZE(children[0]->children); i++)
for (int i = GetSize(id2ast->multirange_dimensions)/1; i < GetSize(children[0]->children); i++)
children.push_back(children[0]->children[i]->clone());
delete children[0];
@ -1366,7 +1366,7 @@ skip_dynamic_range_lvalue_expansion:;
RTLIL::Const arg_value = buf->bitsAsConst();
if (arg_value.as_bool())
arg_value = const_sub(arg_value, 1, false, false, SIZE(arg_value));
arg_value = const_sub(arg_value, 1, false, false, GetSize(arg_value));
delete buf;
uint32_t result = 0;
@ -1455,9 +1455,9 @@ skip_dynamic_range_lvalue_expansion:;
rtype = RTLIL::unescape_id(dpi_decl->children.at(0)->str);
fname = RTLIL::unescape_id(dpi_decl->children.at(1)->str);
for (int i = 2; i < SIZE(dpi_decl->children); i++)
for (int i = 2; i < GetSize(dpi_decl->children); i++)
{
if (i-2 >= SIZE(children))
if (i-2 >= GetSize(children))
log_error("Insufficient number of arguments in DPI function call at %s:%d.\n", filename.c_str(), linenum);
argtypes.push_back(RTLIL::unescape_id(dpi_decl->children.at(i)->str));
@ -1558,7 +1558,7 @@ skip_dynamic_range_lvalue_expansion:;
celltype = RTLIL::escape_id(celltype);
AstNode *cell = new AstNode(AST_CELL, new AstNode(AST_CELLTYPE));
cell->str = prefix.substr(0, SIZE(prefix)-1);
cell->str = prefix.substr(0, GetSize(prefix)-1);
cell->children[0]->str = celltype;
for (auto attr : decl->attributes)
@ -1681,7 +1681,7 @@ skip_dynamic_range_lvalue_expansion:;
bool param_upto = current_scope[str]->range_valid && current_scope[str]->range_swapped;
int param_offset = current_scope[str]->range_valid ? current_scope[str]->range_right : 0;
int param_width = current_scope[str]->range_valid ? current_scope[str]->range_left - current_scope[str]->range_right + 1 :
SIZE(current_scope[str]->children[0]->bits);
GetSize(current_scope[str]->children[0]->bits);
int tmp_range_left = children[0]->range_left, tmp_range_right = children[0]->range_right;
if (param_upto) {
tmp_range_left = (param_width + 2*param_offset) - children[0]->range_right - 1;
@ -1847,7 +1847,7 @@ skip_dynamic_range_lvalue_expansion:;
if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) {
std::vector<AstNode*> new_children;
new_children.push_back(children[0]);
for (int i = 1; i < SIZE(children); i++) {
for (int i = 1; i < GetSize(children); i++) {
AstNode *child = children[i];
log_assert(child->type == AST_COND);
for (auto v : child->children) {
@ -1857,7 +1857,7 @@ skip_dynamic_range_lvalue_expansion:;
continue;
if (v->type == AST_CONSTANT && v->bits_only_01()) {
if (v->bits == children[0]->bits) {
while (i+1 < SIZE(children))
while (i+1 < GetSize(children))
delete children[++i];
goto keep_const_cond;
}

16
frontends/verific/verific.cc
View file

@ -324,7 +324,7 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*,
if (inst->GetCin()->IsGnd()) {
module->addAdd(RTLIL::escape_id(inst->Name()), IN1, IN2, out, SIGNED);
} else {
RTLIL::SigSpec tmp = module->addWire(NEW_ID, SIZE(out));
RTLIL::SigSpec tmp = module->addWire(NEW_ID, GetSize(out));
module->addAdd(NEW_ID, IN1, IN2, tmp, SIGNED);
module->addAdd(RTLIL::escape_id(inst->Name()), tmp, net_map.at(inst->GetCin()), out, false);
}
@ -687,8 +687,8 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
cell->parameters["\\CLK_ENABLE"] = false;
cell->parameters["\\CLK_POLARITY"] = true;
cell->parameters["\\TRANSPARENT"] = false;
cell->parameters["\\ABITS"] = SIZE(addr);
cell->parameters["\\WIDTH"] = SIZE(data);
cell->parameters["\\ABITS"] = GetSize(addr);
cell->parameters["\\WIDTH"] = GetSize(data);
cell->setPort("\\CLK", RTLIL::State::S0);
cell->setPort("\\ADDR", addr);
cell->setPort("\\DATA", data);
@ -709,9 +709,9 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
cell->parameters["\\CLK_ENABLE"] = false;
cell->parameters["\\CLK_POLARITY"] = true;
cell->parameters["\\PRIORITY"] = 0;
cell->parameters["\\ABITS"] = SIZE(addr);
cell->parameters["\\WIDTH"] = SIZE(data);
cell->setPort("\\EN", RTLIL::SigSpec(net_map.at(inst->GetControl())).repeat(SIZE(data)));
cell->parameters["\\ABITS"] = GetSize(addr);
cell->parameters["\\WIDTH"] = GetSize(data);
cell->setPort("\\EN", RTLIL::SigSpec(net_map.at(inst->GetControl())).repeat(GetSize(data)));
cell->setPort("\\CLK", RTLIL::State::S0);
cell->setPort("\\ADDR", addr);
cell->setPort("\\DATA", data);
@ -753,9 +753,9 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
RTLIL::SigSpec conn;
if (cell->hasPort(RTLIL::escape_id(port_name)))
conn = cell->getPort(RTLIL::escape_id(port_name));
while (SIZE(conn) <= port_offset) {
while (GetSize(conn) <= port_offset) {
if (pr->GetPort()->GetDir() != DIR_IN)
conn.append(module->addWire(NEW_ID, port_offset - SIZE(conn)));
conn.append(module->addWire(NEW_ID, port_offset - GetSize(conn)));
conn.append(RTLIL::State::Sz);
}
conn.replace(port_offset, net_map.at(pr->GetNet()));

2
frontends/verilog/parser.y
View file

@ -142,7 +142,7 @@ input: {
ast_stack.push_back(current_ast);
} design {
ast_stack.pop_back();
log_assert(SIZE(ast_stack) == 0);
log_assert(GetSize(ast_stack) == 0);
for (auto &it : default_attr_list)
delete it.second;
default_attr_list.clear();