2311 commits

Author	SHA1	Message	Date
Akash Levy	4bd08ac362	Merge branch 'YosysHQ:main' into main	2025-04-01 22:10:43 -07:00
Miodrag Milanovic	72f2185a94	verific: fix restoring msg state after blackbox import	2025-04-01 17:35:59 +02:00
Akash Levy	d2028feefe	Set Verific flags via -cfg instead of in Yosys	2025-03-25 22:41:06 -07:00
Krystine Sherwin	0a1c664f02	simplify: Skip AST_PRIMITIVE in AST_CELLARRAY ... Otherwise the `AST_PRIMITIVE` simplifies to the corresponding function and is no longer caught by the check for `AST_PRIMITIVE`s, raising an assertion error instead of an input error. Add bug4785.ys to tests/verilog to demonstrate.	2025-03-25 12:15:54 +13:00
Akash Levy	95f489beec	Merge nice gzip refactor	2025-03-20 16:47:12 -07:00
Emil J. Tywoniak	813f909460	gzip: istream	2025-03-19 13:43:44 +01:00
Emil J. Tywoniak	4f3fdc8457	io: refactor string and file work into new unit	2025-03-19 13:43:42 +01:00
Alain Dargelas	3021dab37d	memory limit fix and increased limit	2025-03-17 09:07:33 -07:00
Akash Levy	bc3ca6210c	Add back operator optimization for Verific frontend	2025-03-17 04:06:28 -07:00
Akash Levy	1c0d4a43b3	Merge branch 'YosysHQ:main' into main	2025-03-14 18:07:55 -07:00
Alain Dargelas	88211310fa	code review	2025-03-12 16:32:42 -07:00
Alain Dargelas	dcce15207e	Memory size check	2025-03-12 16:21:18 -07:00
Jason Xu	a5f34d04f8	Address comments	2025-03-11 18:50:44 -04:00
Jason Xu	98eefc5d1a	Add file list support to read pass	2025-03-07 20:44:21 -05:00
Jason Xu	bf1eab565b	Fix compile on WASI platform	2025-03-07 20:20:27 -05:00
Jason Xu	ac31bad656	Address all comments	2025-03-07 20:16:28 -05:00
Jason Xu	8ec96ec806	Address most comments	2025-03-07 20:16:28 -05:00
Jason Xu	0678c4dec9	Coding style update	2025-03-07 20:16:28 -05:00
Jason Xu	f62a9be153	Initial file list support	2025-03-07 20:16:28 -05:00
Akash Levy	881080a827	Merge upstream	2025-03-05 07:54:26 -08:00
Emil J	39aacc95df	Merge pull request #4907 from YosysHQ/emil/fix-clear-preset-latch ... liberty: fix clear and preset latches	2025-03-03 18:53:12 +01:00
Akash Levy	9d3b7f7474	Merge branch 'YosysHQ:main' into main	2025-02-26 09:51:44 -08:00
Martin Povišer	732ed67014	ast/dpicall: Stop using variable length array ... Fix the compiler warning variable length arrays in C++ are a Clang extension [-Wvla-cxx-extension]	2025-02-24 17:32:30 +01:00
Emil J. Tywoniak	2b33937ab8	liberty: fix clear and preset latches	2025-02-17 17:36:51 +01:00
Akash Levy	fd811ddaee	Cleanup	2025-02-14 08:48:27 -08:00
Akash Levy	f76fd9280b	Clean up Verific	2025-02-14 06:56:20 -08:00
Akash Levy	c8c97ea00b	Revert back to using Verific naming	2025-02-13 19:40:33 -08:00
Akash Levy	47aac95f64	Fix incdir, ydir, libext issues	2025-02-05 05:58:49 -08:00
Akash Levy	993b23e747	Merge upstream	2025-02-03 09:33:16 -08:00
KrystalDelusion	cf52cf3009	nowrshmsk: Check for stride==0 ... log2(0) returns -inf, which gives undefined behaviour when casting to an int. So catch the case when it's 0 just set the width to 0.	2025-01-31 12:15:53 +13:00
Akash Levy	bd439fc524	Reapply "Merge upstream" ... This reverts commit e73d51dbf0.	2025-01-23 13:40:32 -08:00
Akash Levy	e73d51dbf0	Revert "Merge upstream" ... This reverts commit c58a50f880, reversing changes made to a1c3c98773.	2025-01-21 05:28:36 -08:00
Akash Levy	c58a50f880	Merge upstream	2025-01-21 04:36:34 -08:00
Akash Levy	a1c3c98773	Messed up usage of SILIMATE_VERIFIC_EXTENSIONS	2025-01-21 00:12:28 -08:00
Akash Levy	da726a4e54	If imported module has parameters it is not a blackbox	2025-01-17 01:14:40 -08:00
N. Engelhardt	d640157ec4	fix some cases of hdlname being added to objects with private names	2025-01-15 15:56:42 +01:00
Akash Levy	57bf3a6f51	Merge branch 'YosysHQ:main' into main	2025-01-14 08:38:59 -08:00
Emil J. Tywoniak	a58481e9b7	mark all hash_into methods nodiscard	2025-01-14 12:39:15 +01:00
Akash Levy	1dcf75d175	Sync	2024-12-19 21:40:30 -08:00
Emil J. Tywoniak	b9b9515bb0	hashlib: hash_eat -> hash_into	2024-12-18 15:09:25 +01:00
Emil J. Tywoniak	4e29ec1854	hashlib: acc -> eat	2024-12-18 15:09:25 +01:00
Emil J. Tywoniak	d071489ab1	hashlib: redo interface for flexibility	2024-12-18 14:49:25 +01:00
Akash Levy	1eee11846e	Resolve reg naming to some extent	2024-12-17 12:11:39 -08:00
Akash Levy	1242db626f	Merge remote-tracking branch 'upstream/main'	2024-12-12 22:49:19 -08:00
N. Engelhardt	378864d33b	bound attributes: handle vhdl null ranges	2024-12-12 11:42:39 +01:00
Akash Levy	caaef5ac14	Merge branch 'YosysHQ:main' into main	2024-12-11 12:00:34 -08:00
N. Engelhardt	03033ab6d4	add more tests for bounds attributes, fix attributes appearing in verilog	2024-12-11 16:11:02 +01:00
Martin Povišer	ea38fcca5e	Merge pull request #4737 from povik/abc_new-design-boxes ... Support `abc9_box` on ordinary modules in abc_new	2024-12-10 20:07:56 +01:00
Martin Povišer	e9c7967d1e	Merge pull request #4804 from povik/read_liberty-comb-cells ... read_liberty: Revisit for abc9 whiteboxes	2024-12-10 17:50:21 +01:00
Martin Povišer	6b343c2600	aiger2: Clean debug print	2024-12-10 14:27:55 +01:00