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Merge upstream

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This commit is contained in:
Akash Levy 2025-01-21 04:36:34 -08:00
commit c58a50f880
15 changed files with 110 additions and 49 deletions
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frontends/verific/verific.cc
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@ -1535,7 +1535,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
log("Importing module %s.\n", RTLIL::id2cstr(module->name));
}
import_attributes(module->attributes, nl, nl);
module->set_string_attribute(ID::hdlname, nl->CellBaseName());
if (module->name.isPublic())
module->set_string_attribute(ID::hdlname, nl->CellBaseName());
module->set_string_attribute(ID(library), nl->Owner()->Owner()->Name());
#ifdef VERIFIC_VHDL_SUPPORT
if (nl->IsFromVhdl()) {