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add more tests for bounds attributes, fix attributes appearing in verilog

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This commit is contained in:
N. Engelhardt 2024-12-11 16:11:02 +01:00
parent e91e95f501
commit 03033ab6d4
4 changed files with 259 additions and 16 deletions
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2
frontends/verific/verific.cc
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@ -433,7 +433,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
auto type_range = nl->GetTypeRange(obj->Name());
if (!type_range)
return;
if (type_range->IsTypeScalar()) {
if (nl->IsFromVhdl() && type_range->IsTypeScalar()) {
const long long bottom_bound = type_range->GetScalarRangeLeftBound();
const long long top_bound = type_range->GetScalarRangeRightBound();
const unsigned bit_width = type_range->NumElements();