Robert O'Callahan
f25f8fe7c4
In the Verilog backend, only sort modules that we're going to emit.
...
If you have a large design with a lot of modules and you use the Verilog
backend to emit modules one at a time to separate files, performance is
very low. The problem is that the Verilog backend calls `design->sort()`
every time, which sorts the contents of all modules, and this is slow
even when everything is already sorted.
We can easily fix this by only sorting the contents of modules that
we're actually going to emit.
2025-07-21 05:32:31 +00:00
github-actions[bot]
aa1daa7023
Bump version
2025-07-18 00:25:48 +00:00
Martin Povišer
9ab1946799
Merge pull request #5209 from povik/hieropt
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Start `opt_hier` to enable hierarchical optimization
2025-07-17 14:12:18 +02:00
Martin Povišer
415b7d3f65
Drop experimental label off synth -hieropt
2025-07-17 12:02:44 +02:00
N. Engelhardt
d009bcc9b6
Merge pull request #5198 from YosysHQ/nak/lcov
2025-07-17 11:57:58 +02:00
N. Engelhardt
beb71a6c47
update short help
2025-07-16 17:11:19 +02:00
N. Engelhardt
fb6974dcd7
print summary of line coverage to log
2025-07-16 13:40:07 +02:00
github-actions[bot]
af0b263557
Bump version
2025-07-16 00:25:58 +00:00
George Rennie
0f40bb3076
Merge pull request #5232 from georgerennie/george/firrtl_name_cache
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write_firrtl: clear used names cache each invocation
2025-07-15 16:49:52 +01:00
Emil J
0f784fd084
Merge pull request #5219 from YosysHQ/emil/fix-liberty-expr-space
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dfflibmap: fix dffe inference when spaces used for ANDs in liberty next_state
2025-07-15 16:39:26 +02:00
George Rennie
381381c997
write_firrtl: clear used names cache each pass
2025-07-15 14:14:07 +01:00
Emil J. Tywoniak
c7a3abbcc4
libparse: LibertyExpression unit test
2025-07-15 12:53:30 +02:00
Emil J. Tywoniak
21e68ec9be
libparse: fix space ANDs
2025-07-15 12:53:13 +02:00
Emil J. Tywoniak
e960428587
unit tests: fix run failure detection
2025-07-15 12:21:01 +02:00
Martin Povišer
46eafa9466
Merge pull request #5230 from whitequark/install-dev
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Allow installing headers and `yosys-config` without the rest
2025-07-15 10:57:41 +02:00
Catherine
62c270a38b
Allow installing headers and yosys-config without the rest.
...
This is useful to be able to build a plugin like `yosys-slang` without
having to build the entirety of Yosys, which can save a lot of time.
2025-07-15 01:28:09 +00:00
Emil J. Tywoniak
bf1f236998
dfflibmap: add back tab and quote filters for good vibes
2025-07-11 23:12:58 +02:00
Emil J. Tywoniak
c6e1d461fa
libparse: support space ANDs
2025-07-11 23:09:30 +02:00
Emil J. Tywoniak
4b1a8a3b66
libparse: add LibertyExpression::str for testing
2025-07-11 18:27:19 +02:00
github-actions[bot]
e57a2b9442
Bump version
2025-07-11 00:25:36 +00:00
Emil J. Tywoniak
6ee01308f2
dfflibmap: show dffe inference is broken by space ANDs
2025-07-11 00:33:01 +02:00
Emil J
dfe86b50d8
Merge pull request #5217 from rocallahan/fix-importSigSpecWorker-leak
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Fix space leak in `SatGen::importSigSpecWorker()` by avoiding `log_id…
2025-07-10 19:56:56 +02:00
Emil J
14aad097f0
Merge pull request #5190 from YosysHQ/emil/dfflibmap-fix-negated-next_state
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dfflibmap: propagate negated next_state to output correctly
2025-07-10 19:50:02 +02:00
Emil J. Tywoniak
7fe817c52f
dfflibmap: test negated state next_state with mixed polarities
2025-07-10 18:54:43 +02:00
N. Engelhardt
02323295b0
Merge pull request #5179 from YosysHQ/krys/assert2cover
2025-07-10 14:53:22 +02:00
N. Engelhardt
d21a553fdc
Merge pull request #5218 from YosysHQ/nak/limit_ub
2025-07-10 14:53:11 +02:00
Emil J. Tywoniak
f34c4f2e26
log: deduplicate unescape_id from log_id
2025-07-09 16:20:27 +02:00
N. Engelhardt
e47f5369fd
verificsva: check -L value is small enough for code to work
2025-07-09 15:58:35 +02:00
Emil J
9334a5c275
Merge pull request #5216 from YosysHQ/emil/publish-libparse-header
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Install libparse.h for use in plugins
2025-07-09 14:28:59 +02:00
github-actions[bot]
7566af4a4b
Bump version
2025-07-09 00:25:57 +00:00
Robert O'Callahan
743df9f0f9
Fix space leak in SatGen::importSigSpecWorker() by avoiding log_id().
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Calling `log_id()` leaks a copy of the ID into `log_id_cache` until the
end of the pass, which causes exorbitant memory usage.
See issue #5210 .
2025-07-08 23:53:38 +00:00
George Rennie
478b6a2b3f
kernel: treat zero width constant as zero
2025-07-08 19:37:59 +01:00
Emil J. Tywoniak
ad80e2bd39
libparse: install headers for use in plugins
2025-07-08 13:39:03 +02:00
Emil J
66035f706e
Merge pull request #5177 from YosysHQ/emil/rename-unescape
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rename: add -unescape
2025-07-08 10:45:11 +02:00
github-actions[bot]
e60cf3e2fa
Bump version
2025-07-08 00:25:06 +00:00
KrystalDelusion
1a215719e5
Merge pull request #5192 from garytwong/multiline-string
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verilog: support newline and hex escapes in string literals
2025-07-08 10:27:01 +12:00
Emil J. Tywoniak
658c7dd424
rename: fix help
2025-07-07 16:16:57 +02:00
Miodrag Milanovic
8af60b7e17
Next dev cycle
2025-07-07 12:40:53 +02:00
Miodrag Milanovic
60f126cd00
Release version 0.55
2025-07-07 11:26:04 +02:00
Emil J
468cbb800c
Merge pull request #5206 from yrabbit/cell-creation-script-5a
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Gowin. BUGFIX. Fix multi-line descriptions.
2025-07-07 10:36:42 +02:00
N. Engelhardt
642756a9c6
Merge pull request #5178 from jix/sva_cover_only_followed_by
2025-07-07 10:07:06 +02:00
Martin Povišer
62067cd6cb
Update docs after addition of new pass
2025-07-05 16:45:52 +02:00
Martin Povišer
22a44e4333
Start opt_hier
2025-07-05 16:45:52 +02:00
github-actions[bot]
99f7d79abb
Bump version
2025-07-05 00:23:55 +00:00
Miodrag Milanović
afd0ba0099
Merge pull request #5208 from YosysHQ/micko/replace_const_exprs
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verific: enable replacing const exprs in static elaboration by default
2025-07-04 10:35:03 +02:00
Gary Wong
5feb1a1752
verilog: add support for SystemVerilog string literals.
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Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-07-03 20:51:12 -06:00
Miodrag Milanovic
eed3bc243f
verific: enable replacing const exprs in static elaboration by default
2025-07-02 11:54:19 +02:00
YRabbit
85e7c68fc6
Gowin. BUGFIX. Fix multi-line descriptions.
...
If let's say the enumeration of inputs took several lines, then all
after the first one were ignored. Since the first line ended with a
comma, an error was generated when trying to use the resulting file.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-07-02 12:39:18 +10:00
N. Engelhardt
8a4f465143
update test to use suggested selection for assertions
2025-07-01 11:46:27 +02:00
N. Engelhardt
7b0c1fe491
Merge pull request #5102 from YosysHQ/krys/verilog_no_select
2025-06-30 13:35:17 +00:00
