Robert O'Callahan
dcd7742d52
Avoid scanning entire module if there are no wires to remove
...
It's pretty common for `opt_clean` to find no wires to remove. In that case,
there is no point scanning the entire design, which can be significantly
expensive for huge designs.
2026-01-23 01:38:20 +00:00
Robert O'Callahan
e87bb65956
Move Design::sort() calls out of opt and opt_clean passes into the synth passes that need them.
2026-01-23 01:14:35 +00:00
KrystalDelusion
125609105d
Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix
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abc: handle ABC script errors instead of hanging
2026-01-23 07:16:48 +13:00
KrystalDelusion
98f848e503
Merge pull request #5546 from YosysHQ/krys/nested_packages
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Document nesting packages as unsupported
2026-01-23 07:16:22 +13:00
github-actions[bot]
a6fc695522
Bump version
2026-01-22 00:28:34 +00:00
Emil J
317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon
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Add debugon pass for persistent debug logging
2026-01-21 17:34:30 +01:00
Emil J
5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree
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Add opt_balance_tree pass
2026-01-21 17:34:08 +01:00
nella
f6eba53d1f
Fix copyright header.
2026-01-21 14:52:19 +01:00
nella
2c12545cf3
opt_dff restructure.
2026-01-21 10:08:44 +01:00
Miodrag Milanović
2157f9b3fb
Merge pull request #5622 from rocallahan/spurious-copy
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Avoid spurious copy in `IdStringCollector::trace_named()`
2026-01-21 08:30:07 +01:00
Robert O'Callahan
2c0448a81b
Avoid spurious copy in IdStringCollector::trace_named()
2026-01-21 03:31:56 +00:00
github-actions[bot]
57ac113b7f
Bump version
2026-01-21 00:27:51 +00:00
Gus Smith
9ed56ac72c
Mimic pattern of how other tests build plugins
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Seems like using --build isn't supported in CI
2026-01-20 10:44:47 -08:00
Gus Smith
bd9dbea4ea
Add -I
2026-01-20 10:07:44 -08:00
Gus Smith
0f6ef77775
Add test for ezCmdlineSAT
2026-01-20 09:28:00 -08:00
Gabriel Gouvine
979b673f20
ezsat: Fix handling of error codes
2026-01-20 07:54:50 -08:00
Gabriel Gouvine
d2b6bd00b1
ezsat: Rename files and class for ezCmdlineSat
2026-01-20 07:54:50 -08:00
Gabriel Gouvine
6565bf3ebf
ezsat: Fix build for emscripten/wasi
2026-01-20 07:54:50 -08:00
Gabriel Gouvine
12315c0d17
ezsat: Support for assumptions in Sat command
2026-01-20 07:54:49 -08:00
Gabriel Gouvine
9315f02c17
ezsat: New Sat class to call an external command
2026-01-20 07:54:49 -08:00
Miodrag Milanović
bfd1401b32
Merge pull request #5612 from YosysHQ/sv2017
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verific: add explicit System Verilog 2017 option
2026-01-20 14:44:46 +01:00
Miodrag Milanovic
d0fa4781c6
verific: Fix -sv2017 message and formatting
2026-01-20 08:07:26 +01:00
Gus Smith
491276983e
Add test
2026-01-19 18:34:55 -08:00
Martin Povišer
90673cb0a2
techmap: Use -icells mode of frontend instead of type fixup
2026-01-19 16:49:49 -08:00
Martin Povišer
f67d4bcfa4
verilog: Do not set module_not_derived on internal cells
2026-01-19 16:48:13 -08:00
github-actions[bot]
49e5950791
Bump version
2026-01-20 00:26:10 +00:00
Krystine Sherwin
0f478a5952
tests/bug5574: Fix for non threaded abc
2026-01-20 05:56:14 +13:00
Miodrag Milanovic
cc3038f468
verific: Fix -sv2017 message
2026-01-19 16:32:46 +01:00
Miodrag Milanović
2bde91b6ef
Merge pull request #5618 from YosysHQ/update_abc
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Update ABC as per 2026-01-19
2026-01-19 15:45:02 +01:00
nella
67d10a41e8
Merge pull request #5617 from YosysHQ/emil/consteval-description
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consteval: describe
2026-01-19 14:56:24 +01:00
Miodrag Milanovic
691983be14
Update ABC as per 2026-01-19
2026-01-19 12:08:24 +01:00
Emil J
7880f31acb
Merge pull request #5531 from YosysHQ/emil/shuffle-contributing-docs
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docs: shuffle and expand contributing info
2026-01-19 12:02:49 +01:00
Emil J. Tywoniak
c3f36afe7f
opt_balance_tree: mark experimental
2026-01-19 12:01:25 +01:00
Emil J. Tywoniak
befadf6d4d
consteval: describe
2026-01-19 12:00:18 +01:00
Miodrag Milanović
9355fa5037
Merge pull request #5616 from rocallahan/fix-unused-var-warning
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Fix warning about unused variable in `dffunmap`.
2026-01-19 08:24:48 +01:00
Robert O'Callahan
28c199fbbd
Fix warning about unused variable in dffunmap.
2026-01-19 03:25:09 +00:00
KrystalDelusion
8da8d681d0
Merge pull request #5544 from YosysHQ/krys/sim_check_eval_err
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Improve error handling in sim
2026-01-19 09:51:12 +13:00
Natalia
b43c96b03d
fix pyosys Design.run_pass binding to use Pass::call signature
2026-01-18 02:24:36 -08:00
Natalia
cf511628b0
modify generator for pyosys/wrappers.cc instead of headers
2026-01-18 02:11:09 -08:00
Miodrag Milanovic
d095d2c405
verific: add explicit System Verilog 2017 option
2026-01-16 07:56:53 +01:00
Natalia
ed64df737b
Add -on/-off modes to debug pass
2026-01-15 12:07:26 -08:00
Natalia
d5e1647d11
fix tests with truncation issues
2026-01-14 18:03:30 -08:00
Natalia
fb864e91ee
Add Design::run_pass() API for programmatic pass execution
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This commit adds a new run_pass() method to the RTLIL::Design class,
providing a convenient API for executing Yosys passes programmatically.
This is particularly useful for PyYosys users who want to run passes
on a design object without needing to manually construct Pass::call()
invocations. The method wraps Pass::call() with appropriate logging
to maintain consistency with command-line pass execution.
Example usage (from Python):
design = ys.Design()
# ... build or load design ...
design.run_pass("hierarchy")
design.run_pass("proc")
design.run_pass("opt")
Changes:
- kernel/rtlil.h: Add run_pass() method declaration
- kernel/rtlil.cc: Implement run_pass() method
- tests/unit/kernel/test_design_run_pass.cc: Add unit tests
2026-01-14 17:35:45 -08:00
github-actions[bot]
967b47d984
Bump version
2026-01-15 00:24:54 +00:00
Natalia
305b6c81d7
Refine width check to allow Y_WIDTH >= natural width
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Change from equality check to >= to allow cells where output
is wider than natural width (zero-extended). Only reject cells
with Y_WIDTH < natural width (truncated).
This fixes test failures while still preventing the truncation
issue identified in widlarizer's feedback.
2026-01-14 14:58:53 -08:00
Natalia
60ac3670cb
Fix truncation issue in opt_balance_tree pass
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Only allow rebalancing of cells with "natural" output widths (no truncation).
This prevents equivalence failures when moving operands between adders
with different intermediate truncation points.
For each operation type, the natural width is:
- Addition: max(A_WIDTH, B_WIDTH) + 1 (for carry bit)
- Multiplication: A_WIDTH + B_WIDTH
- Logic ops: max(A_WIDTH, B_WIDTH)
Fixes widlarizer's counterexample in YosysHQ/yosys#5605 where an 8-bit
intermediate wire was intentionally truncating adder results, and
rebalancing would change where that truncation occurred.
2026-01-14 13:14:56 -08:00
Emil J. Tywoniak
ddf3c6c8b7
blif: add -gatesi test
2026-01-14 21:41:56 +01:00
kamay
e0077b188d
Add gatesi_mode in BLIF format
2026-01-14 21:41:56 +01:00
nella
763001885f
Merge pull request #5608 from YosysHQ/nella/rtlil-to-string
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Add rtlil string getters
2026-01-14 19:00:47 +01:00
nella
210b733555
Add rtlil string getters
2026-01-14 15:37:18 +01:00
