Emil J. Tywoniak
e690fb59f1
docs: fix verilog frontend internals
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
56058b3ed4
read_verilog, ast: use unified locations in errors and simplify dependencies
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
41d9a1b88e
readme, verilog_parser: bison 3.8 and ubuntu 22.04 example
2025-07-10 21:15:50 +02:00
Krystine Sherwin
7e026d824a
dpicall.cc: Fix sans-plugin function call
2025-07-10 21:15:50 +02:00
Krystine Sherwin
cf0f72dbd7
Makefile: Add flex lib/include for brew
2025-07-10 21:15:50 +02:00
Krystine Sherwin
a2b2188a7f
preproc.cc: Use full path for generated file
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Fixes out-of-tree builds.
2025-07-10 21:15:50 +02:00
Krystine Sherwin
b90622b7ed
docs/verilog_frontend.rst: Fix indentation
2025-07-10 21:15:50 +02:00
Krystine Sherwin
7b5035e0c4
preproc depends on parser
2025-07-10 21:15:50 +02:00
Krystine Sherwin
c70224a68a
Add libfl-dev
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Should fix the missing `<FlexLexer.h>` error.
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
040d717ad7
fixup! fixup! ast, read_verilog: unify location types, reduce filename copying
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
ed0582c9f2
fixup! ast, read_verilog: unify location types, reduce filename copying
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
81e5270484
ast, read_verilog: unify location types, reduce filename copying
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
b276fb6616
neater errors, lost in the sauce of source
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
88800a16ea
ast, read_verilog: refactoring
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
31002cf259
ast: fix new memory safety bugs from rebase
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
6cb789b2c2
ast: ownership for string values
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
8a873a7724
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
bb08919105
Revert "verilog: fix string literal regular expression ( #5187 )"
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This reverts commit 834a7294b7
2025-07-10 21:15:38 +02:00
Emil J. Tywoniak
dc204dc909
Revert "verilog: add support for SystemVerilog string literals."
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This reverts commit 5feb1a1752
2025-07-10 21:14:38 +02:00
Emil J. Tywoniak
e0822c048e
Revert "verilog: fix parser "if" memory errors."
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This reverts commit 34a2abeddb
2025-07-10 21:13:28 +02:00
Emil J
dfe86b50d8
Merge pull request #5217 from rocallahan/fix-importSigSpecWorker-leak
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Fix space leak in `SatGen::importSigSpecWorker()` by avoiding `log_id…
2025-07-10 19:56:56 +02:00
Emil J
14aad097f0
Merge pull request #5190 from YosysHQ/emil/dfflibmap-fix-negated-next_state
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dfflibmap: propagate negated next_state to output correctly
2025-07-10 19:50:02 +02:00
Emil J. Tywoniak
7fe817c52f
dfflibmap: test negated state next_state with mixed polarities
2025-07-10 18:54:43 +02:00
N. Engelhardt
02323295b0
Merge pull request #5179 from YosysHQ/krys/assert2cover
2025-07-10 14:53:22 +02:00
N. Engelhardt
d21a553fdc
Merge pull request #5218 from YosysHQ/nak/limit_ub
2025-07-10 14:53:11 +02:00
Emil J. Tywoniak
f34c4f2e26
log: deduplicate unescape_id from log_id
2025-07-09 16:20:27 +02:00
N. Engelhardt
e47f5369fd
verificsva: check -L value is small enough for code to work
2025-07-09 15:58:35 +02:00
Emil J
9334a5c275
Merge pull request #5216 from YosysHQ/emil/publish-libparse-header
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Install libparse.h for use in plugins
2025-07-09 14:28:59 +02:00
github-actions[bot]
7566af4a4b
Bump version
2025-07-09 00:25:57 +00:00
Robert O'Callahan
743df9f0f9
Fix space leak in SatGen::importSigSpecWorker() by avoiding log_id().
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Calling `log_id()` leaks a copy of the ID into `log_id_cache` until the
end of the pass, which causes exorbitant memory usage.
See issue #5210 .
2025-07-08 23:53:38 +00:00
George Rennie
478b6a2b3f
kernel: treat zero width constant as zero
2025-07-08 19:37:59 +01:00
Emil J. Tywoniak
ad80e2bd39
libparse: install headers for use in plugins
2025-07-08 13:39:03 +02:00
Emil J
66035f706e
Merge pull request #5177 from YosysHQ/emil/rename-unescape
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rename: add -unescape
2025-07-08 10:45:11 +02:00
github-actions[bot]
e60cf3e2fa
Bump version
2025-07-08 00:25:06 +00:00
KrystalDelusion
1a215719e5
Merge pull request #5192 from garytwong/multiline-string
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verilog: support newline and hex escapes in string literals
2025-07-08 10:27:01 +12:00
Emil J. Tywoniak
658c7dd424
rename: fix help
2025-07-07 16:16:57 +02:00
Miodrag Milanovic
8af60b7e17
Next dev cycle
2025-07-07 12:40:53 +02:00
Miodrag Milanovic
60f126cd00
Release version 0.55
2025-07-07 11:26:04 +02:00
Emil J
468cbb800c
Merge pull request #5206 from yrabbit/cell-creation-script-5a
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Gowin. BUGFIX. Fix multi-line descriptions.
2025-07-07 10:36:42 +02:00
N. Engelhardt
642756a9c6
Merge pull request #5178 from jix/sva_cover_only_followed_by
2025-07-07 10:07:06 +02:00
github-actions[bot]
99f7d79abb
Bump version
2025-07-05 00:23:55 +00:00
Miodrag Milanović
afd0ba0099
Merge pull request #5208 from YosysHQ/micko/replace_const_exprs
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verific: enable replacing const exprs in static elaboration by default
2025-07-04 10:35:03 +02:00
Gary Wong
5feb1a1752
verilog: add support for SystemVerilog string literals.
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Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-07-03 20:51:12 -06:00
Miodrag Milanovic
eed3bc243f
verific: enable replacing const exprs in static elaboration by default
2025-07-02 11:54:19 +02:00
YRabbit
85e7c68fc6
Gowin. BUGFIX. Fix multi-line descriptions.
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If let's say the enumeration of inputs took several lines, then all
after the first one were ignored. Since the first line ended with a
comma, an error was generated when trying to use the resulting file.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-07-02 12:39:18 +10:00
N. Engelhardt
7b0c1fe491
Merge pull request #5102 from YosysHQ/krys/verilog_no_select
2025-06-30 13:35:17 +00:00
Miodrag Milanović
54013c6da7
Merge pull request #5162 from YosysHQ/micko/attrmap
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Make attrmap able to alter memory attributes as well
2025-06-30 15:24:04 +02:00
github-actions[bot]
67583fee48
Bump version
2025-06-30 00:27:10 +00:00
KrystalDelusion
74575691a0
Merge pull request #5180 from YosysHQ/krys/test_asan
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Add ASAN to CI
2025-06-30 10:40:34 +12:00
Krystine Sherwin
017524d7a2
tests/verific: Don't ASAN verific
2025-06-28 11:33:18 +12:00
