3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-15 03:35:40 +00:00
Commit graph

2816 commits

Author SHA1 Message Date
Mohamed Gaber
e58125b605
Merge remote-tracking branch 'upstream/main' into silimate 2026-06-09 16:22:51 +03:00
Miodrag Milanović
693d5a7eb0
Merge pull request #5903 from YosysHQ/krys/verific_memsize
verific: Fix non-contiguous memory flattening producing out of bounds accesses in some cases
2026-06-04 05:43:04 +00:00
Miodrag Milanovic
ce280354cf Update CI scripts for CMake
Co-authored-by: Catherine <whitequark@whitequark.org>
2026-06-03 08:58:11 +00:00
Catherine
a727e7f6e7 Migrate build system to CMake
See #5895 for details.

This commit does not include CI or documentation changes.
2026-06-03 08:58:10 +00:00
Catherine
bcc736ed7d Revert "Putting back some Makefile.conf"
This reverts commit d8587f44f0.
2026-06-02 15:01:50 +00:00
Akash Levy
b3ea5770cd opt_argmax pass 2026-06-02 04:11:17 -07:00
Akash Levy
c7b2c16405
Merge pull request #179 from Silimate/opt_compact_prefix
Add opt_compact_prefix pass
2026-06-02 02:14:37 -07:00
Akash Levy
a730032f5f Add opt_compact_prefix pass 2026-06-01 23:00:33 -07:00
Akash Levy
0c3446e8af Fixups for Greptile 2026-06-01 19:03:52 -07:00
Akash Levy
9cc69a3c49 Improvement to opt_balance_tree 2026-06-01 17:56:44 -07:00
Philippe Sauter
c89cfe1e6e peepopt: add shiftpow2 pattern
Rewrite power-of-two indexed word selects to $bmux when the shift
amount already carries the scale as low zero bits.

Keep the rule to non-overlapping selections and bound the generated
mux ways. Add regressions for aligned shifts, padding, signed
extension, and shiftmul handoff cases.
2026-05-31 02:01:32 +02:00
Krystine Sherwin
0360a4bd0a
tests/check_mem: Drop unused init check
It was also raising an error in `read_verilog`.
2026-05-30 11:06:11 +12:00
Emil J. Tywoniak
80bdbaa010 genrtlil: don't avoid emitting flops for nosync 2026-05-29 11:37:08 +02:00
Krystine Sherwin
52e0030cc5
tests/check_mem: Add problematic case
Verific reports it as 16 2-bit addresses, meaning we have to iterate over the last dimension while skipping indices.
2026-05-29 18:40:25 +12:00
Krystine Sherwin
ab5f25db9a
Add test for non-contiguous memory init
Also negative memory addresses.
2026-05-29 18:40:24 +12:00
Krystine Sherwin
aac7366862
tests: Add check_mem to vanilla-test 2026-05-29 18:40:24 +12:00
Krystine Sherwin
f6327cc444
check_mem: Add -non-const option
Can identify potentially dangerous addressing, but also prone to false-positives.
2026-05-29 18:40:24 +12:00
Krystine Sherwin
07e3d648aa
Add check_mem command
Comes with a set of tests which (currently) pass with `read_verilog` but fail with `verific` based on #5878.
Add `--check-sv`, an alternative to `--prove-sv` with generator defined yosys commands.  Helpful for when you want to run the same set of commands on a bunch of sv files.
2026-05-29 18:40:23 +12:00
Miodrag Milanović
1801abf30a
Merge pull request #5913 from YosysHQ/abcexternal
Putting back some Makefile.conf
2026-05-28 09:49:16 +00:00
Miodrag Milanovic
d8587f44f0 Putting back some Makefile.conf 2026-05-28 11:13:29 +02:00
nella
d6106f141c Add matching for fused mac operations for Nexus (fix #5906). 2026-05-28 09:58:18 +02:00
Akash Levy
14efbe3ee6 Smallfix 2026-05-27 04:36:45 -07:00
Akash Levy
6a8d800e63 Fixes for filtering small cases and catching more larger ones with trickier signatures 2026-05-27 03:40:44 -07:00
Akash Levy
5c3fbd2d63 Merge branch 'main' into opt_addcin 2026-05-27 01:52:11 -07:00
Akash Levy
89717069fe Fixup 2026-05-27 01:51:54 -07:00
Akash Levy
d3c5591647
Merge pull request #171 from Silimate/infer_icg
infer_icg pass
2026-05-27 01:06:40 -07:00
Akash Levy
7ea578a212
Merge pull request #170 from Silimate/ffnormpol
ffnormpol pass
2026-05-27 01:05:05 -07:00
Akash Levy
e39395132d opt_addcin pass 2026-05-27 00:39:25 -07:00
Akash Levy
2bb10837d9 infer_icg pass 2026-05-27 00:14:51 -07:00
Akash Levy
9e73dd6d27 ffnormpol pass 2026-05-27 00:13:05 -07:00
Akash Levy
42d257e523 opt_andor_pmux pass 2026-05-27 00:11:54 -07:00
junyao
6f111118de proc: ignore nosync temporaries in always_latch checks 2026-05-26 00:56:07 +08:00
Akash Levy
2ba8a5cac6 opt parallel prefix and priority encoders 2026-05-20 12:14:50 -07:00
Akash Levy
b4e94d9f13 modshr onehot pass 2026-05-20 01:25:28 -07:00
Miodrag Milanovic
4c8e61a52b Expose SBY binary location 2026-05-19 16:08:21 +02:00
Miodrag Milanovic
07924a3c62 Use common.mk for sva tests as well 2026-05-19 15:15:41 +02:00
Miodrag Milanovic
2b3f4c37f5 Fix functional tests 2026-05-19 14:42:08 +02:00
Miodrag Milanovic
15e09163cd Do not use Makefile.conf 2026-05-19 14:29:06 +02:00
Miodrag Milanovic
c0779f488a Make out of tree build testing possible 2026-05-19 14:26:07 +02:00
Emil J. Tywoniak
1c831aa50d threading: whitespace 2026-05-18 16:26:14 +02:00
Miodrag Milanovic
4a4c3a3be6 Make better validation 2026-05-18 08:50:38 +02:00
Miodrag Milanovic
ef092e1f15 Include conf so individual test running works 2026-05-18 08:50:20 +02:00
Leon White
59c1bc35cb Fix aiger tests when ABCEXTERNAL is set 2026-05-16 09:12:20 +02:00
Miodrag Milanovic
1ef6311e5b Update documentation and few more defines 2026-05-13 11:24:45 +02:00
Miodrag Milanovic
7fe32137bd Revert "Fix tests due to ABC improvements"
This reverts commit 417e871b06.
2026-05-11 14:47:08 +02:00
Emil J
1f02343268
Merge pull request #5817 from YosysHQ/emil/clockgate-reject-sdffe
clockgate: reject $sdffe to fix priority handling
2026-05-08 18:38:51 +00:00
Emil J. Tywoniak
425d47ad2c clockgate: test $sdffe rejected 2026-05-07 16:13:14 +02:00
Emil J. Tywoniak
687e5442f2 clockgate: formal liberty tests 2026-05-07 16:08:55 +02:00
Emil J
4e35ed5955
Merge pull request #5827 from cdleary/cdleary/2026-04-21-sv-positional-assignment-unpacked
Support positional assignment patterns for unpacked arrays
2026-05-07 10:55:17 +00:00
Lofty
ab316c14d2
Merge pull request #5844 from YosysHQ/lofty/abc-refactor-5
abc_new: integration testing via synth_gatemate
2026-05-06 13:40:15 +00:00