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https://github.com/YosysHQ/yosys
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modshr onehot pass
This commit is contained in:
Akash Levy
parent
242d87079a
commit
b4e94d9f13
4 changed files with 473 additions and 7 deletions
338
tests/peepopt/modshr_onehot.ys
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338
tests/peepopt/modshr_onehot.ys
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log -header "Positive: mbase MSB one-hot (8'b1000_0000), shiftamt 3 bits"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [11:0] a,
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input [2:0] shiftamt,
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output [11:0] y
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);
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localparam [7:0] MBASE = 8'b1000_0000;
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assign y = a % (MBASE >> shiftamt);
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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opt_clean
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select -assert-count 0 t:$mod
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select -assert-count 1 t:$and
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select -assert-count 1 t:$shr
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design -reset
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log -pop
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log -header "Positive: mbase non-MSB one-hot (8'b0010_0000)"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [11:0] a,
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input [1:0] shiftamt,
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output [11:0] y
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);
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localparam [7:0] MBASE = 8'b0010_0000;
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assign y = a % (MBASE >> shiftamt);
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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opt_clean
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select -assert-count 0 t:$mod
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select -assert-count 1 t:$and
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select -assert-count 1 t:$shr
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design -reset
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log -pop
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log -header "Positive: shiftamt clog2(N) bits, divisor never zero (mbase = 1<<(N-1))"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [15:0] a,
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input [3:0] shiftamt,
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output [15:0] y
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);
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localparam [15:0] MBASE = 16'h8000;
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assign y = a % (MBASE >> shiftamt);
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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opt_clean
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select -assert-count 0 t:$mod
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select -assert-count 1 t:$and
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select -assert-count 1 t:$shr
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design -reset
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log -pop
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log -header "Positive: low-position one-hot, shiftamt bounded so divisor != 0"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [7:0] a,
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input shiftamt,
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output [7:0] y
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);
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localparam [7:0] MBASE = 8'b0000_0010;
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assign y = a % (MBASE >> shiftamt);
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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opt_clean
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select -assert-count 0 t:$mod
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select -assert-count 1 t:$and
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select -assert-count 1 t:$shr
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design -reset
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log -pop
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log -header "Positive: wider mbase than a, shiftamt sized so divisor != 0"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [3:0] a,
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input [1:0] shiftamt,
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output [3:0] y
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);
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localparam [7:0] MBASE = 8'b0001_0000;
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assign y = a % (MBASE >> shiftamt);
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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opt_clean
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select -assert-count 0 t:$mod
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select -assert-count 1 t:$and
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select -assert-count 1 t:$shr
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design -reset
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log -pop
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log -header "Positive: \$shr A_SIGNED=1 (signed parameter), Y wider than mod->B"
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log -push
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design -reset
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read_verilog -sv <<EOT
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module top(
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input [11:0] a,
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input [1:0] shiftamt,
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output [11:0] y
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);
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// FIFO_DEPTH is inferred as a signed integer parameter, so the
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// synthesized \$shr cell ends up with A_SIGNED=1 even though the
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// value is positive. Verilog also widens the shifter Y to 32 bits;
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// only the low bits feed the modulo. shiftamt range 0..3 keeps
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// (FIFO_DEPTH >> shiftamt) in {32,16,8,4} -- never zero.
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parameter FIFO_DEPTH = 32;
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wire [5:0] divisor = FIFO_DEPTH >> shiftamt;
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assign y = a % divisor;
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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opt_clean
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select -assert-count 0 t:$mod
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select -assert-count 1 t:$and
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select -assert-count 1 t:$shr
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design -reset
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log -pop
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log -header "Positive: shared shifter Y fans out to many \$mod cells (generate loop)"
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log -push
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design -reset
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read_verilog -sv <<EOT
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module top(
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input [11:0] a0, a1, a2, a3,
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input [1:0] shiftamt,
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output [11:0] y0, y1, y2, y3
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);
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parameter FIFO_DEPTH = 32;
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wire [5:0] divisor = FIFO_DEPTH >> shiftamt;
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assign y0 = a0 % divisor;
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assign y1 = a1 % divisor;
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assign y2 = a2 % divisor;
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assign y3 = a3 % divisor;
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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opt_clean
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select -assert-count 0 t:$mod
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select -assert-count 4 t:$and
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# 4 mask shifters + 1 original (still drives the shared divisor wire
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# whose remaining bits may be dead). opt_clean keeps the original
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# while any of its Y bits has a name attached; check >= 4 shifters.
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select -assert-min 4 t:$shr
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design -reset
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log -pop
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log -header "Positive: rewrite still applied even when divisor can be 0; assert via peepopt only"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [7:0] a,
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input [2:0] shiftamt,
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output [7:0] y
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);
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localparam [7:0] MBASE = 8'b0000_0001;
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assign y = a % (MBASE >> shiftamt);
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endmodule
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EOT
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check -assert
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peepopt
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opt_clean
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select -assert-count 0 t:$mod
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select -assert-count 1 t:$and
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select -assert-count 1 t:$shr
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design -reset
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log -pop
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log -header "Negative: mbase is NOT one-hot (8'b0011_0000)"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [11:0] a,
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input [2:0] shiftamt,
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output [11:0] y
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);
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localparam [7:0] MBASE = 8'b0011_0000;
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assign y = a % (MBASE >> shiftamt);
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$mod
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select -assert-count 0 t:$and
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design -reset
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log -pop
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log -header "Negative: mbase is a wire (not constant) -- pattern must not match"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [11:0] a,
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input [7:0] mbase,
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input [2:0] shiftamt,
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output [11:0] y
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);
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assign y = a % (mbase >> shiftamt);
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$mod
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design -reset
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log -pop
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log -header "Negative: signed dividend (A_SIGNED=1 on $mod)"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input signed [11:0] a,
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input [2:0] shiftamt,
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output signed [11:0] y
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);
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localparam signed [7:0] MBASE = 8'b0010_0000;
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assign y = a % $signed(MBASE >> shiftamt);
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$mod
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design -reset
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log -pop
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log -header "Negative: shifter is $shl (left shift) -- not the right pattern"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [11:0] a,
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input [2:0] shiftamt,
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output [11:0] y
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);
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localparam [7:0] MBASE = 8'b0000_0001;
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assign y = a % (MBASE << shiftamt);
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$mod
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design -reset
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log -pop
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log -header "Positive: shifter Y also drives an external probe (extra fanout OK)"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [11:0] a,
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input [1:0] shiftamt,
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output [11:0] y,
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output [7:0] probe
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);
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localparam [7:0] MBASE = 8'b0010_0000;
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wire [7:0] divisor = MBASE >> shiftamt;
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assign y = a % divisor;
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assign probe = divisor;
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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opt_clean
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# The original $shr must be preserved because it drives \probe; the
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# rewrite only retargets the $mod, replacing it with $and + a new mask
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# shifter.
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select -assert-count 0 t:$mod
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select -assert-count 1 t:$and
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select -assert-count 2 t:$shr
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design -reset
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log -pop
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log -header "Negative: B_SIGNED=1 on $mod with one-hot at MSB of mbase"
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log -push
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design -reset
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read_verilog <<EOT
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module top(
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input [11:0] a,
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input [2:0] shiftamt,
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output [11:0] y
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);
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wire signed [7:0] divisor = $signed(8'b1000_0000) >>> shiftamt;
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assign y = a % divisor;
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endmodule
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EOT
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check -assert
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equiv_opt -assert peepopt
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design -load postopt
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select -assert-count 1 t:$mod
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design -reset
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log -pop
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