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Make out of tree build testing possible

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This commit is contained in:
Miodrag Milanovic 2026-05-19 14:26:07 +02:00
parent 5c6de04467
commit c0779f488a
37 changed files with 131 additions and 119 deletions
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2
tests/Makefile
View file

@ -100,7 +100,7 @@ makefile-./%: %/Makefile
.PHONY: functional
functional:
ifeq ($(ENABLE_FUNCTIONAL_TESTS),1)
@cd functional && ./run-test.sh
-@cd functional && ./run-test.sh
endif
vanilla-test: prep makefile-tests functional

4
tests/arch/xilinx/macc.sh
View file

@ -1,6 +1,6 @@
../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v
${YOSYS} -qp "synth_xilinx -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v
iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v
vvp -N ./test_macc
../../../yosys -qp "synth_xilinx -family xc6s -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v
${YOSYS} -qp "synth_xilinx -family xc6s -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v
iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v
vvp -N ./test_macc

4
tests/arch/xilinx/tribuf.sh
View file

@ -1,5 +1,5 @@
../../../yosys -f verilog -qp "synth_xilinx" ../common/tribuf.v
../../../yosys -f verilog -qp "synth_xilinx -iopad; \
${YOSYS} -f verilog -qp "synth_xilinx" ../common/tribuf.v
${YOSYS} -f verilog -qp "synth_xilinx -iopad; \
select -assert-count 2 t:IBUF; \
select -assert-count 1 t:INV; \
select -assert-count 1 t:OBUFT" ../common/tribuf.v

2
tests/bram/run-single.sh
View file

@ -1,6 +1,6 @@
#!/usr/bin/env bash
set -e
../../yosys -qq -f verilog -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \
${YOSYS} -qq -f verilog -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \
-l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v
iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1 -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \
temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v

20
tests/bugpoint/failures.ys
View file

@ -1,29 +1,29 @@
write_file fail.temp << EOF
logger -expect error "Missing -script or -command option." 1
bugpoint -suffix fail -yosys ../../yosys
bugpoint -suffix fail -yosys ${YOSYS}
EOF
exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp
exec -expect-return 0 -- ${YOSYS} -qq mods.il -s fail.temp
write_file fail.temp << EOF
logger -expect error "do not crash on this design" 1
bugpoint -suffix fail -yosys ../../yosys -command "dump"
bugpoint -suffix fail -yosys ${YOSYS} -command "dump"
EOF
exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp
exec -expect-return 0 -- ${YOSYS} -qq mods.il -s fail.temp
write_file fail.temp << EOF
logger -expect error "returned value 3 instead of expected 7" 1
bugpoint -suffix fail -yosys ../../yosys -command raise_error -expect-return 7
bugpoint -suffix fail -yosys ${YOSYS} -command raise_error -expect-return 7
EOF
exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp
exec -expect-return 0 -- ${YOSYS} -qq mods.il -s fail.temp
write_file fail.temp << EOF
logger -expect error "not found in the log file!" 1
bugpoint -suffix fail -yosys ../../yosys -command raise_error -grep "nope"
bugpoint -suffix fail -yosys ${YOSYS} -command raise_error -grep "nope"
EOF
exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp
exec -expect-return 0 -- ${YOSYS} -qq mods.il -s fail.temp
write_file fail.temp << EOF
logger -expect error "not found in stderr log!" 1
bugpoint -suffix fail -yosys ../../yosys -command raise_error -err-grep "nope"
bugpoint -suffix fail -yosys ${YOSYS} -command raise_error -err-grep "nope"
EOF
exec -expect-return 0 -- ../../yosys -qq mods.il -s fail.temp
exec -expect-return 0 -- ${YOSYS} -qq mods.il -s fail.temp

20
tests/bugpoint/mod_constraints.ys
View file

@ -6,35 +6,35 @@ design -stash base
# everything is removed by default
design -load base
bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
bugpoint -suffix mods -yosys ${YOSYS} -command raise_error -expect-return 3
select -assert-count 1 w:*
select -assert-mod-count 1 =*
select -assert-none c:*
# don't remove wires
design -load base
bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -modules -cells
bugpoint -suffix mods -yosys ${YOSYS} -command raise_error -expect-return 3 -modules -cells
select -assert-count 3 w:*
select -assert-mod-count 1 =*
select -assert-none c:*
# don't remove cells or their connections
design -load base
bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -wires -modules
bugpoint -suffix mods -yosys ${YOSYS} -command raise_error -expect-return 3 -wires -modules
select -assert-count 5 w:*
select -assert-mod-count 1 =*
select -assert-count 4 c:*
# don't remove cells but do remove their connections
design -load base
bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -wires -modules -connections
bugpoint -suffix mods -yosys ${YOSYS} -command raise_error -expect-return 3 -wires -modules -connections
select -assert-count 1 w:*
select -assert-mod-count 1 =*
select -assert-count 4 c:*
# don't remove modules
design -load base
bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3 -wires -cells
bugpoint -suffix mods -yosys ${YOSYS} -command raise_error -expect-return 3 -wires -cells
select -assert-count 1 w:*
select -assert-mod-count 3 =*
select -assert-none c:*
@ -42,7 +42,7 @@ select -assert-none c:*
# can keep wires
design -load base
setattr -set bugpoint_keep 1 w:w_b
bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
bugpoint -suffix mods -yosys ${YOSYS} -command raise_error -expect-return 3
select -assert-count 2 w:*
select -assert-mod-count 1 =*
select -assert-none c:*
@ -50,7 +50,7 @@ select -assert-none c:*
# a wire with keep won't keep the cell/module containing it
design -load base
setattr -set bugpoint_keep 1 w:w_o
bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
bugpoint -suffix mods -yosys ${YOSYS} -command raise_error -expect-return 3
select -assert-count 1 w:*
select -assert-mod-count 1 =*
select -assert-none c:*
@ -58,7 +58,7 @@ select -assert-none c:*
# can keep cells (and do it without the associated module)
design -load base
setattr -set bugpoint_keep 1 c:c_a
bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
bugpoint -suffix mods -yosys ${YOSYS} -command raise_error -expect-return 3
select -assert-count 1 w:*
select -assert-mod-count 1 =*
select -assert-count 1 c:*
@ -66,7 +66,7 @@ select -assert-count 1 c:*
# can keep modules
design -load base
setattr -mod -set bugpoint_keep 1 m_a
bugpoint -suffix mods -yosys ../../yosys -command raise_error -expect-return 3
bugpoint -suffix mods -yosys ${YOSYS} -command raise_error -expect-return 3
select -assert-count 1 w:*
select -assert-mod-count 2 =*
select -assert-none c:*
@ -77,7 +77,7 @@ write_file script.temp << EOF
select -assert-none w:w_a %co* w:w_c %ci* %i
EOF
design -load base
bugpoint -suffix mods -yosys ../../yosys -script script.temp -grep "Assertion failed"
bugpoint -suffix mods -yosys ${YOSYS} -script script.temp -grep "Assertion failed"
select -assert-count 5 w:*
select -assert-mod-count 2 =*
select -assert-count 2 c:*

14
tests/bugpoint/proc_constraints.ys
View file

@ -4,18 +4,18 @@ design -stash err_q
# processes get removed by default
design -load err_q
bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4
bugpoint -suffix procs -yosys ${YOSYS} -command raise_error -expect-return 4
select -assert-none p:*
# individual processes can be kept
design -load err_q
setattr -set bugpoint_keep 1 p:proc_a
bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4
bugpoint -suffix procs -yosys ${YOSYS} -command raise_error -expect-return 4
select -assert-count 1 p:*
# all processes can be kept
design -load err_q
bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -wires
bugpoint -suffix procs -yosys ${YOSYS} -command raise_error -expect-return 4 -wires
select -assert-count 2 p:*
# d and clock are connected after proc
@ -26,24 +26,24 @@ select -assert-count 3 w:clock %co
# no assigns means no d
design -load err_q
bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -assigns
bugpoint -suffix procs -yosys ${YOSYS} -command raise_error -expect-return 4 -assigns
proc
select -assert-count 1 w:d %co
# no updates means no clock
design -load err_q
bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -updates
bugpoint -suffix procs -yosys ${YOSYS} -command raise_error -expect-return 4 -updates
proc
select -assert-count 1 w:clock %co
# can remove ports
design -load err_q
select -assert-count 5 x:*
bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -ports
bugpoint -suffix procs -yosys ${YOSYS} -command raise_error -expect-return 4 -ports
select -assert-none x:*
# can keep ports
design -load err_q
setattr -set bugpoint_keep 1 i:d o:q
bugpoint -suffix procs -yosys ../../yosys -command raise_error -expect-return 4 -ports
bugpoint -suffix procs -yosys ${YOSYS} -command raise_error -expect-return 4 -ports
select -assert-count 2 x:*

14
tests/bugpoint/raise_error.ys
View file

@ -24,21 +24,21 @@ logger -check-expected
design -load read
setattr -mod -unset raise_error def other
dump
bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 7
bugpoint -suffix error -yosys ${YOSYS} -command raise_error -expect-return 7
select -assert-mod-count 1 =*
select -assert-mod-count 1 top
# raise_error -always still uses 'raise_error' attribute if possible
design -load read
setattr -mod -unset raise_error def other
bugpoint -suffix error -yosys ../../yosys -command "raise_error -always" -expect-return 7
bugpoint -suffix error -yosys ${YOSYS} -command "raise_error -always" -expect-return 7
select -assert-mod-count 1 =*
select -assert-mod-count 1 top
# raise_error with string prints message and exits with 1
design -load read
setattr -mod -unset raise_error top def
bugpoint -suffix error -yosys ../../yosys -command raise_error -grep "help me" -expect-return 1
bugpoint -suffix error -yosys ${YOSYS} -command raise_error -grep "help me" -expect-return 1
select -assert-mod-count 1 =*
select -assert-mod-count 1 other
@ -46,18 +46,18 @@ select -assert-mod-count 1 other
design -load read
setattr -mod -unset raise_error top
delete other
bugpoint -suffix error -yosys ../../yosys -command raise_error -expect-return 1
bugpoint -suffix error -yosys ${YOSYS} -command raise_error -expect-return 1
select -assert-mod-count 1 =*
select -assert-mod-count 1 def
# raise_error -stderr prints to stderr and exits with 1
design -load read
setattr -mod -unset raise_error top def
bugpoint -suffix error -yosys ../../yosys -command "raise_error -stderr" -err-grep "help me" -expect-return 1
bugpoint -suffix error -yosys ${YOSYS} -command "raise_error -stderr" -err-grep "help me" -expect-return 1
select -assert-mod-count 1 =*
select -assert-mod-count 1 other
# empty design can raise_error -always
design -reset
bugpoint -suffix error -yosys ../../yosys -command "raise_error -always" -grep "ERROR: No 'raise_error' attribute found" -expect-return 1
bugpoint -suffix error -yosys ../../yosys -command "raise_error -always -stderr" -err-grep "No 'raise_error' attribute found" -expect-return 1
bugpoint -suffix error -yosys ${YOSYS} -command "raise_error -always" -grep "ERROR: No 'raise_error' attribute found" -expect-return 1
bugpoint -suffix error -yosys ${YOSYS} -command "raise_error -always -stderr" -err-grep "No 'raise_error' attribute found" -expect-return 1

12
tests/common.mk
View file

@ -1,3 +1,15 @@
ROOT_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
BUILD_DIR ?= $(ROOT_DIR)/..
YOSYS ?= $(BUILD_DIR)/yosys
ABC ?= $(BUILD_DIR)/yosys-abc
YOSYS_FILTERLIB ?= $(BUILD_DIR)/yosys-filterlib
YOSYS_CONFIG ?= $(BUILD_DIR)/yosys-config
export YOSYS
export YOSYS_CONFIG
export ABC
all:
ifndef OVERRIDE_MAIN

6
tests/functional/test_functional.py
View file

@ -1,6 +1,6 @@
import subprocess
import pytest
import sys
import os
import shlex
from pathlib import Path
@ -18,7 +18,7 @@ def run(cmd, **kwargs):
assert status.returncode == 0, f"{cmd[0]} failed"
def yosys(script):
run([base_path / 'yosys', '-Q', '-p', script])
run([os.environ.get("YOSYS", "../../yosys"), '-Q', '-p', script])
def compile_cpp(in_path, out_path, args):
run(['g++', '-g', '-std=c++20'] + args + [str(in_path), '-o', str(out_path)])
@ -35,7 +35,7 @@ def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""):
# since yosys sim aborts on simulation mismatch to generate vcd output
# we have to re-run with a different set of flags
# on this run we ignore output and return code, we just want a best-effort attempt to get a vcd
subprocess.run([base_path / 'yosys', '-Q', '-p',
subprocess.run([os.environ.get("YOSYS", "../../yosys"), '-Q', '-p',
f'read_rtlil {quote(rtlil_file)}; sim -vcd {quote(vcd_out_file)} -a -r {quote(vcd_reference_file)} -scope gold -timescale 1us -fst-noinit'],
capture_output=True, check=False)
raise

4
tests/gen_tests_makefile.py
View file

@ -97,7 +97,7 @@ def print_header(extra=None):
print(f"ifneq ($(wildcard {yosys_basedir}/Makefile.conf),)")
print(f"include {yosys_basedir}/Makefile.conf")
print(f"endif")
print(f"YOSYS ?= {yosys_basedir}/yosys")
print("")
print("export YOSYS_MAX_THREADS := 4")
if extra:
@ -128,7 +128,7 @@ def generate_custom(callback, extra=None):
callback()
def generate_autotest_file(test_file, commands):
cmd = f"../tools/autotest.sh -G -j ${{SEEDOPT}} ${{EXTRA_FLAGS}} {test_file}; \\\n{commands}"
cmd = f"../tools/autotest.sh -G -j ${{SEEDOPT}} -Y ${{YOSYS}} ${{EXTRA_FLAGS}} {test_file}; \\\n{commands}"
generate_target(test_file, cmd)
def generate_autotest(pattern, extra_flags, cmds=""):

3
tests/liberty/generate_mk.py
View file

@ -36,8 +36,7 @@ def main():
lib_tests()
ys_tests()
gen_tests_makefile.generate_custom(callback,
[f"YOSYS_FILTERLIB ?= {gen_tests_makefile.yosys_basedir}/yosys-filterlib"])
gen_tests_makefile.generate_custom(callback)
if __name__ == "__main__":

6
tests/memfile/generate_mk.py
View file

@ -40,19 +40,19 @@ def create_tests():
gen_tests_makefile.generate_cmd_test("child_content1", [
f"{setup}",
'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v; '
'cd temp && $(YOSYS) -qp "read_verilog -defer ../memory.v; '
'chparam -set MEMFILE \\"content1.dat\\" memory"'
])
gen_tests_makefile.generate_cmd_test("child_content2_temp", [
f"{setup}",
'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v; '
'cd temp && $(YOSYS) -qp "read_verilog -defer ../memory.v; '
'chparam -set MEMFILE \\"temp/content2.dat\\" memory"'
])
gen_tests_makefile.generate_cmd_test("child_content2_direct", [
f"{setup}",
'cd temp && ../$(YOSYS) -qp "read_verilog -defer ../memory.v; '
'cd temp && $(YOSYS) -qp "read_verilog -defer ../memory.v; '
'chparam -set MEMFILE \\"temp/content2.dat\\" memory"'
])

2
tests/memlib/generate_mk.py
View file

@ -1574,7 +1574,7 @@ def create_tests():
for lib in t.libs:
libs_args += f" -l memlib_{lib}.v"
cmd = (
f"../tools/autotest.sh -G -j ${{SEEDOPT}} ${{EXTRA_FLAGS}} "
f"../tools/autotest.sh -G -j ${{SEEDOPT}} -Y ${{YOSYS}} "
f"-p 'script ../t_{t.name}.ys'"
f"{libs_args} "
f"t_{t.name}.v || (cat t_{t.name}.err; exit 1)"

2
tests/rpc/frontend.py
View file

@ -87,7 +87,7 @@ def main():
sock.bind(args.path)
try:
sock.listen(1)
ys_proc = subprocess.Popen(["../../yosys", "-ql", "unix.log", "-p", "connect_rpc -path {}; read_verilog design.v; hierarchy -top top; flatten; select -assert-count 1 t:$neg".format(args.path)])
ys_proc = subprocess.Popen([os.environ.get("YOSYS", "../../yosys"), "-ql", "unix.log", "-p", "connect_rpc -path {}; read_verilog design.v; hierarchy -top top; flatten; select -assert-count 1 t:$neg".format(args.path)])
conn, addr = sock.accept()
file = conn.makefile("rw")
while True:

5
tests/rtlil/roundtrip-design.sh
View file

@ -1,10 +1,9 @@
set -euo pipefail
YS=../../yosys
mkdir -p temp
$YS -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-push.il; design -push; design -pop; write_rtlil temp/roundtrip-design-pop.il"
${YOSYS} -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-push.il; design -push; design -pop; write_rtlil temp/roundtrip-design-pop.il"
diff temp/roundtrip-design-push.il temp/roundtrip-design-pop.il
$YS -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-save.il; design -save foo; design -load foo; write_rtlil temp/roundtrip-design-load.il"
${YOSYS} -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-save.il; design -save foo; design -load foo; write_rtlil temp/roundtrip-design-load.il"
diff temp/roundtrip-design-save.il temp/roundtrip-design-load.il

7
tests/rtlil/roundtrip-text.sh
View file

@ -1,5 +1,4 @@
set -euo pipefail
YS=../../yosys
mkdir -p temp
@ -11,7 +10,7 @@ remove_empty_lines() {
}
# write_rtlil and dump are equivalent
$YS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.write.il"
${YOSYS} -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.write.il"
remove_empty_lines temp/roundtrip-text.dump.il
remove_empty_lines temp/roundtrip-text.write.il
# Trim first line ("Generated by Yosys ...")
@ -19,13 +18,13 @@ tail -n +2 temp/roundtrip-text.write.il > temp/roundtrip-text.write-nogen.il
diff temp/roundtrip-text.dump.il temp/roundtrip-text.write-nogen.il
# Loading and writing it out again doesn't change the RTLIL
$YS -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload.il"
${YOSYS} -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload.il"
remove_empty_lines temp/roundtrip-text.reload.il
tail -n +2 temp/roundtrip-text.reload.il > temp/roundtrip-text.reload-nogen.il
diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-nogen.il
# Hashing differences don't change the RTLIL
$YS --hash-seed=2345678 -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload-hash.il"
${YOSYS} --hash-seed=2345678 -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload-hash.il"
remove_empty_lines temp/roundtrip-text.reload-hash.il
tail -n +2 temp/roundtrip-text.reload-hash.il > temp/roundtrip-text.reload-hash-nogen.il
diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-hash-nogen.il

2
tests/sdc/side-effects.sh
View file

@ -1,4 +1,4 @@
#!/usr/bin/env bash
../../yosys -p 'read_verilog alu_sub.v; proc; hierarchy -auto-top; sdc side-effects.sdc' | grep 'This should print something:
${YOSYS} -p 'read_verilog alu_sub.v; proc; hierarchy -auto-top; sdc side-effects.sdc' | grep 'This should print something:
YOSYS_SDC_MAGIC_NODE_0'

2
tests/sdc/unknown-getter.sh
View file

@ -2,4 +2,4 @@
set -euo pipefail
! ../../yosys -p 'read_verilog alu_sub.v; proc; hierarchy -auto-top; sdc get_foo.sdc' 2>&1 | grep 'Unknown getter'
! ${YOSYS} -p 'read_verilog alu_sub.v; proc; hierarchy -auto-top; sdc get_foo.sdc' 2>&1 | grep 'Unknown getter'

8
tests/sva/runtest.sh
View file

@ -59,7 +59,7 @@ generate_sby() {
if [ -f $prefix.ys ]; then
set -x
$PWD/../../yosys -q -e "Assert .* failed." -s $prefix.ys
${YOSYS} -q -e "Assert .* failed." -s $prefix.ys
elif [ -f $prefix.sv ]; then
generate_sby pass > ${prefix}_pass.sby
generate_sby fail > ${prefix}_fail.sby
@ -67,8 +67,8 @@ elif [ -f $prefix.sv ]; then
# Check that SBY is up to date enough for this yosys version
if sby --help | grep -q -e '--status'; then
set -x
sby --yosys $PWD/../../yosys -f ${prefix}_pass.sby
sby --yosys $PWD/../../yosys -f ${prefix}_fail.sby
sby --yosys ${YOSYS} -f ${prefix}_pass.sby
sby --yosys ${YOSYS} -f ${prefix}_fail.sby
else
echo "sva test '${prefix}' requires an up to date SBY, skipping"
fi
@ -78,7 +78,7 @@ else
# Check that SBY is up to date enough for this yosys version
if sby --help | grep -q -e '--status'; then
set -x
sby --yosys $PWD/../../yosys -f ${prefix}.sby
sby --yosys ${YOSYS} -f ${prefix}.sby
else
echo "sva test '${prefix}' requires an up to date SBY, skipping"
fi

2
tests/techmap/bug5495.sh
View file

@ -5,7 +5,7 @@ if ! which timeout ; then
exit 0
fi
if ! timeout 10 ../../yosys bug5495.v -p 'hierarchy; techmap; abc -script bug5495.abc' ; then
if ! timeout 10 ${YOSYS} bug5495.v -p 'hierarchy; techmap; abc -script bug5495.abc' ; then
echo "Yosys failed to complete"
exit 1
fi

2
tests/techmap/mem_simple_4x1_runtest.sh
View file

@ -1,3 +1,3 @@
#!/usr/bin/env bash
exec ../tools/autotest.sh -G -j $@ -p 'proc; opt; memory -nomap; techmap -map ../mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v
exec ../tools/autotest.sh -G -Y ${YOSYS} -j $@ -p 'proc; opt; memory -nomap; techmap -map ../mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v

2
tests/techmap/recursive_runtest.sh
View file

@ -1,3 +1,3 @@
set -e
../../yosys -p 'read_verilog recursive.v; hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar'
${YOSYS} -p 'read_verilog recursive.v; hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar'

11
tests/tools/autotest.sh
View file

@ -24,6 +24,7 @@ warn_iverilog_git=false
firrtl2verilog=""
xfirrtl="../xfirrtl"
abcprog="$toolsdir/../../yosys-abc"
yosysprog="$toolsdir/../../yosys"
exec {lock}<"$toolsdir"; flock "$lock" 1>&2
if [ ! -f "$toolsdir/cmp_tbdata" -o "$toolsdir/cmp_tbdata.c" -nt "$toolsdir/cmp_tbdata" ]; then
@ -31,7 +32,7 @@ if [ ! -f "$toolsdir/cmp_tbdata" -o "$toolsdir/cmp_tbdata.c" -nt "$toolsdir/cmp_
fi
flock -u "$lock"; exec {lock}>&-
while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do
while getopts xmGl:wkjvref:s:p:n:S:I:A:Y:-: opt; do
case "$opt" in
x)
use_xsim=true ;;
@ -70,6 +71,8 @@ while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do
minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
A)
abcprog="$OPTARG" ;;
Y)
yosysprog="$OPTARG" ;;
-)
case "${OPTARG}" in
xfirrtl)
@ -159,7 +162,7 @@ do
fi
if [ ! -f ../${bn}_tb.v ]; then
"$toolsdir"/../../yosys -f "$frontend $include_opts -D_AUTOTB" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext}
$yosysprog -f "$frontend $include_opts -D_AUTOTB" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext}
else
cp ../${bn}_tb.v ${bn}_tb.v
fi
@ -173,7 +176,7 @@ do
test_count=0
test_passes() {
"$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@"
$yosysprog -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@"
touch ${bn}.iverilog
compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
${bn}_tb.v ${bn}_syn${test_count}.v "${libs[@]}" \
@ -203,7 +206,7 @@ do
test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${refext}
if [ -n "$firrtl2verilog" ]; then
if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext}
$yosysprog -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext}
$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v
test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine" ${bn}_ref.fir.v
fi

8
tests/various/async.sh
View file

@ -1,9 +1,9 @@
#!/usr/bin/env bash
set -ex
../../yosys -q -o async_syn.v -r uut -p 'synth; rename uut syn' async.v
../../yosys -q -o async_prp.v -r uut -p 'prep; rename uut prp' async.v
../../yosys -q -o async_a2s.v -r uut -p 'prep; async2sync; rename uut a2s' async.v
../../yosys -q -o async_ffl.v -r uut -p 'prep; clk2fflogic; rename uut ffl' async.v
${YOSYS} -q -o async_syn.v -r uut -p 'synth; rename uut syn' async.v
${YOSYS} -q -o async_prp.v -r uut -p 'prep; rename uut prp' async.v
${YOSYS} -q -o async_a2s.v -r uut -p 'prep; async2sync; rename uut a2s' async.v
${YOSYS} -q -o async_ffl.v -r uut -p 'prep; clk2fflogic; rename uut ffl' async.v
iverilog -o async_sim -DTESTBENCH async.v async_???.v
vvp -N async_sim > async.out
tail async.out

8
tests/various/chparam.sh
View file

@ -35,18 +35,18 @@ module top #(
endmodule
EOT
if ../../yosys -q -p 'verific -sv chparam1.sv'; then
../../yosys -q -p 'verific -sv chparam1.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
if ${YOSYS} -q -p 'verific -sv chparam1.sv'; then
${YOSYS} -q -p 'verific -sv chparam1.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
-p 'async2sync' \
-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
../../yosys -q -p 'verific -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
${YOSYS} -q -p 'verific -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
-p 'async2sync' \
-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'
fi
../../yosys -q -p 'read_verilog -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
${YOSYS} -q -p 'read_verilog -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \
-p 'async2sync' \
-p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \
-p 'sat -falsify -prove-asserts -show-ports -set din[0] 0'

4
tests/various/clk2fflogic_effects.sh
View file

@ -3,14 +3,14 @@ set -e
# TODO: when sim gets native $check support, remove the -DNO_ASSERT here
echo Running yosys sim
../../yosys -q -p "
${YOSYS} -q -p "
read_verilog -formal -DNO_ASSERT clk2fflogic_effects.sv
hierarchy -top top; proc;;
tee -q -o clk2fflogic_effects.sim.log sim -q -n 32
"
echo Running yosys clk2fflogic sim
../../yosys -q -p "
${YOSYS} -q -p "
read_verilog -formal clk2fflogic_effects.sv
hierarchy -top top; proc;;
clk2fflogic;;

8
tests/various/ezcmdline_plugin.sh
View file

@ -4,9 +4,9 @@ DIR=$(cd "$(dirname "$0")" && pwd)
BASEDIR=$(cd "$DIR/../.." && pwd)
rm -f "$DIR/ezcmdline_plugin.so"
chmod +x "$DIR/ezcmdline_dummy_solver"
CXXFLAGS=$("$BASEDIR/yosys-config" --cxxflags)
DATDIR=$("$BASEDIR/yosys-config" --datdir)
CXXFLAGS=$(${YOSYS_CONFIG} --cxxflags)
DATDIR=$(${YOSYS_CONFIG} --datdir)
DATDIR=${DATDIR//\//\\\/}
CXXFLAGS=${CXXFLAGS//$DATDIR/..\/..\/share}
"$BASEDIR/yosys-config" --exec --cxx ${CXXFLAGS} -I"$BASEDIR" --ldflags -shared -o "$DIR/ezcmdline_plugin.so" "$DIR/ezcmdline_plugin.cc"
"$BASEDIR/yosys" -m "$DIR/ezcmdline_plugin.so" -p "ezcmdline_test -cmd $DIR/ezcmdline_dummy_solver" | grep -q "ezcmdline_test passed!"
${YOSYS_CONFIG} --exec --cxx ${CXXFLAGS} -I"$BASEDIR" --ldflags -shared -o "$DIR/ezcmdline_plugin.so" "$DIR/ezcmdline_plugin.cc"
${YOSYS} -m "$DIR/ezcmdline_plugin.so" -p "ezcmdline_test -cmd $DIR/ezcmdline_dummy_solver" | grep -q "ezcmdline_test passed!"

6
tests/various/hierarchy.sh
View file

@ -4,7 +4,7 @@
set -e
echo -n " TOP first - "
../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
${YOSYS} -s - <<- EOY | grep "Automatically selected TOP as design top module"
read_verilog << EOV
module TOP(a, y);
input a;
@ -23,7 +23,7 @@ echo -n " TOP first - "
EOY
echo -n " TOP last - "
../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
${YOSYS} -s - <<- EOY | grep "Automatically selected TOP as design top module"
read_verilog << EOV
module aoi12(a, y);
input a;
@ -42,7 +42,7 @@ echo -n " TOP last - "
EOY
echo -n " no explicit top - "
../../yosys -s - <<- EOY | grep "Automatically selected noTop as design top module."
${YOSYS} -s - <<- EOY | grep "Automatically selected noTop as design top module."
read_verilog << EOV
module aoi12(a, y);
input a;

2
tests/various/logger_cmd_error.sh
View file

@ -2,7 +2,7 @@
trap 'echo "ERROR in logger_cmd_error.sh" >&2; exit 1' ERR
(../../yosys -v 3 -C <<EOF
(${YOSYS} -v 3 -C <<EOF
yosys -import
hierarchy -top nonexistent
EOF

2
tests/various/logger_fail.sh
View file

@ -10,7 +10,7 @@ runTest() {
want="$2"
shift 2
echo "running '$desc' with args $@"
output=`../../yosys -q "$@" 2>&1`
output=`${YOSYS} -q "$@" 2>&1`
if [ $? -ne 1 ]; then
fail "exit code for '$desc' was not 1"
fi

10
tests/various/plugin.sh
View file

@ -1,12 +1,12 @@
set -e
rm -f plugin.so
rm -rf plugin_search
CXXFLAGS=$(../../yosys-config --cxxflags)
DATDIR=$(../../yosys-config --datdir)
CXXFLAGS=$(${YOSYS_CONFIG} --cxxflags)
DATDIR=$(${YOSYS_CONFIG} --datdir)
DATDIR=${DATDIR//\//\\\/}
CXXFLAGS=${CXXFLAGS//$DATDIR/..\/..\/share}
../../yosys-config --exec --cxx ${CXXFLAGS} --ldflags -shared -o plugin.so plugin.cc
../../yosys -m ./plugin.so -p "test" | grep -q "Plugin test passed!"
${YOSYS_CONFIG} --exec --cxx ${CXXFLAGS} --ldflags -shared -o plugin.so plugin.cc
${YOSYS} -m ./plugin.so -p "test" | grep -q "Plugin test passed!"
mkdir -p plugin_search
mv plugin.so plugin_search/plugin.so
YOSYS_PLUGIN_PATH=$PWD/plugin_search ../../yosys -m plugin.so -p "test" | grep -q "Plugin test passed!"
YOSYS_PLUGIN_PATH=$PWD/plugin_search ${YOSYS} -m plugin.so -p "test" | grep -q "Plugin test passed!"

20
tests/various/sv_implicit_ports.sh
View file

@ -3,7 +3,7 @@
trap 'echo "ERROR in sv_implicit_ports.sh" >&2; exit 1' ERR
# Simple case
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
@ -15,7 +15,7 @@ endmodule
EOT
# Generate block
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
@ -31,7 +31,7 @@ endmodule
EOT
# Missing wire
((../../yosys -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
((${YOSYS} -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
@ -43,7 +43,7 @@ EOT
) 2>&1 | grep -F "ERROR: No matching wire for implicit port connection \`b' of cell top.add_i (add)." > /dev/null
# Incorrectly sized wire
((../../yosys -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
((${YOSYS} -f "verilog -sv" -qp "hierarchy -top top" - || true) <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
@ -56,7 +56,7 @@ EOT
) 2>&1 | grep -F "ERROR: Width mismatch between wire (7 bits) and port (8 bits) for implicit port connection \`b' of cell top.add_i (add)." > /dev/null
# Defaults
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a = 8'd00, input [7:0] b = 8'd01, output [7:0] q);
assign q = a + b;
endmodule
@ -67,7 +67,7 @@ endmodule
EOT
# Parameterised module
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add #(parameter N=3) (input [N-1:0] a = 8'd00, input [N-1:0] b = 8'd01, output [N-1:0] q);
assign q = a + b;
endmodule
@ -78,7 +78,7 @@ endmodule
EOT
# Parameterised blackbox module
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - <<EOT
${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - <<EOT
(* blackbox *)
module add #(parameter N=3) (input [N-1:0] a, b, output [N-1:0] q);
endmodule
@ -89,7 +89,7 @@ endmodule
EOT
# Parameterised blackbox module - incorrect width
((../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - || true) <<EOT
((${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:add" - || true) <<EOT
(* blackbox *)
module add #(parameter N=3) (input [N-1:0] a, b, output [N-1:0] q);
endmodule
@ -101,7 +101,7 @@ EOT
) 2>&1 | grep -F "ERROR: Width mismatch between wire (8 bits) and port (6 bits) for implicit port connection \`q' of cell top.add_i (add)." > /dev/null
# Mixed implicit and explicit 1
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule
@ -112,7 +112,7 @@ endmodule
EOT
# Mixed implicit and explicit 2
(../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
(${YOSYS} -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a, input [7:0] b, output [7:0] q);
assign q = a + b;
endmodule

10
tests/various/svalways.sh
View file

@ -3,7 +3,7 @@
trap 'echo "ERROR in svalways.sh" >&2; exit 1' ERR
# Good case
../../yosys -f "verilog -sv" -qp proc - <<EOT
${YOSYS} -f "verilog -sv" -qp proc - <<EOT
module top(input clk, en, d, output reg p, q, r);
always_ff @(posedge clk)
@ -19,7 +19,7 @@ endmodule
EOT
# Incorrect always_comb syntax
((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
((${YOSYS} -f "verilog -sv" -qp proc -|| true) <<EOT
module top(input d, output reg q);
always_comb @(d)
@ -30,7 +30,7 @@ EOT
) 2>&1 | grep -F "<stdin>:3: ERROR: syntax error, unexpected '@'" > /dev/null
# Incorrect use of always_comb
((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
((${YOSYS} -f "verilog -sv" -qp proc -|| true) <<EOT
module top(input en, d, output reg q);
always_comb
@ -41,7 +41,7 @@ EOT
) 2>&1 | grep -F "ERROR: Latch inferred for signal \`\\top.\\q' from always_comb process" > /dev/null
# Incorrect use of always_latch
((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
((${YOSYS} -f "verilog -sv" -qp proc -|| true) <<EOT
module top(input en, d, output reg q);
always_latch
@ -52,7 +52,7 @@ EOT
) 2>&1 | grep -F "ERROR: No latch inferred for signal \`\\top.\\q' from always_latch process" > /dev/null
# Incorrect use of always_ff
((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT
((${YOSYS} -f "verilog -sv" -qp proc -|| true) <<EOT
module top(input en, d, output reg q);
always_ff @(*)

2
tests/verilog/dynamic_range_lhs.sh
View file

@ -7,7 +7,7 @@ run() {
right=$4
echo "a=$alt s=$span l=$left r=$right"
../../yosys -q \
${YOSYS} -q \
-DALT=$alt \
-DSPAN=$span \
-DLEFT=$left \

12
tests/verilog/local_include.sh
View file

@ -3,7 +3,7 @@
set -eu
# only works with read_verilog
yosys='../../yosys -f verilog'
yosyscmd="${YOSYS} -f verilog"
test='-p hierarchy'
subdir=subdir
source=local_include.v
@ -11,20 +11,20 @@ include=temp_foo.v
# no include file should fail
rm -f $include
echo "logger -expect error $include 1; read_verilog $source" | $yosys
echo "logger -expect error $include 1; read_verilog $source" | $yosyscmd
# both files local
echo 'module foo (input a, output b); assign b = a; endmodule' > $include
$yosys $test $source
$yosyscmd $test $source
# include local to cwd
mkdir -p $subdir
cp $source $subdir
$yosys $test $subdir/$source
$yosyscmd $test $subdir/$source
# include local to source
mv $include $subdir
$yosys $test $subdir/$source
$yosyscmd $test $subdir/$source
# include local to source, and source is given as an absolute path
$yosys $test $(pwd)/$subdir/$source
$yosyscmd $test $(pwd)/$subdir/$source

2
tests/xprop/test.py
View file

@ -47,7 +47,7 @@ if "clean" in steps:
def yosys(command):
subprocess.check_call(["../../../yosys", "-Qp", command])
subprocess.check_call([os.environ.get("YOSYS", "../../yosys"), "-Qp", command])
def remove(file):
try: