547 commits

Author	SHA1	Message	Date
Akash Levy	fd811ddaee	Cleanup	2025-02-14 08:48:27 -08:00
Akash Levy	f76fd9280b	Clean up Verific	2025-02-14 06:56:20 -08:00
Akash Levy	c8c97ea00b	Revert back to using Verific naming	2025-02-13 19:40:33 -08:00
Akash Levy	47aac95f64	Fix incdir, ydir, libext issues	2025-02-05 05:58:49 -08:00
Akash Levy	bd439fc524	Reapply "Merge upstream" ... This reverts commit e73d51dbf0.	2025-01-23 13:40:32 -08:00
Akash Levy	e73d51dbf0	Revert "Merge upstream" ... This reverts commit c58a50f880, reversing changes made to a1c3c98773.	2025-01-21 05:28:36 -08:00
Akash Levy	c58a50f880	Merge upstream	2025-01-21 04:36:34 -08:00
Akash Levy	a1c3c98773	Messed up usage of SILIMATE_VERIFIC_EXTENSIONS	2025-01-21 00:12:28 -08:00
Akash Levy	da726a4e54	If imported module has parameters it is not a blackbox	2025-01-17 01:14:40 -08:00
N. Engelhardt	d640157ec4	fix some cases of hdlname being added to objects with private names	2025-01-15 15:56:42 +01:00
Akash Levy	1dcf75d175	Sync	2024-12-19 21:40:30 -08:00
Emil J. Tywoniak	d071489ab1	hashlib: redo interface for flexibility	2024-12-18 14:49:25 +01:00
Akash Levy	1eee11846e	Resolve reg naming to some extent	2024-12-17 12:11:39 -08:00
Akash Levy	1242db626f	Merge remote-tracking branch 'upstream/main'	2024-12-12 22:49:19 -08:00
N. Engelhardt	378864d33b	bound attributes: handle vhdl null ranges	2024-12-12 11:42:39 +01:00
N. Engelhardt	03033ab6d4	add more tests for bounds attributes, fix attributes appearing in verilog	2024-12-11 16:11:02 +01:00
Akash Levy	e0ba08dd1d	Merge branch 'YosysHQ:main' into main	2024-12-09 11:13:47 -08:00
Miodrag Milanovic	7d4aff618f	verific: Disable module existence check during static elaboration	2024-12-06 15:59:09 +01:00
Akash Levy	7847b1b2eb	Merge pull request #30 from alaindargelas/macro_power ... Simulation information for macro power	2024-12-04 10:01:04 -08:00
Alain Dargelas	350b04daa3	Ignore unused modules	2024-12-03 13:00:14 -08:00
Akash Levy	e0cef06b52	Merge branch 'YosysHQ:main' into main	2024-12-02 19:39:14 -05:00
Miodrag Milanovic	912b38eedb	verific: Handle crash when using empty box option	2024-12-02 15:45:12 +01:00
Akash Levy	ead4b34c3c	Add stack include to decorate_loops.h	2024-12-01 16:50:51 -05:00
Akash Levy	620bf51c50	Merge pull request #29 from alaindargelas/loop_info_3 ... Selective boolopt	2024-12-01 12:36:09 -05:00
Akash Levy	6e88c689f2	Merge branch 'YosysHQ:main' into main	2024-12-01 12:32:07 -05:00
Alain Dargelas	c32d0a412c	Selective boolopt	2024-11-25 15:08:42 -08:00
Miodrag Milanović	29e8812bab	Merge pull request #4724 from YosysHQ/micko/blackbox_verific ... verific: fix blackbox regression and add test case	2024-11-25 15:06:54 +01:00
Akash Levy	c3d6821f7d	Removing compiler warnings and errors	2024-11-22 20:04:39 -08:00
Alain Dargelas	97f5ef2056	indent	2024-11-21 11:31:36 -08:00
Alain Dargelas	dc9d61ed61	Loop info	2024-11-21 11:24:00 -08:00
Alain Dargelas	179bd25235	Loop info	2024-11-21 11:23:13 -08:00
Alain Dargelas	dde6a8d8f1	Loop info	2024-11-21 11:20:40 -08:00
Miodrag Milanovic	d6bd521487	verific : VHDL assert DFF initial value set on Verific library patch side	2024-11-21 13:43:26 +01:00
Akash Levy	bbbc292209	Smallfixes	2024-11-20 21:10:58 -08:00
Akash Levy	6a7e2d2572	Beginnings of UPF support	2024-11-20 20:36:29 -08:00
Akash Levy	2b39770f57	Update flags to be better	2024-11-20 20:36:12 -08:00
Akash Levy	6be73e5c2e	Updates	2024-11-15 19:02:06 -08:00
Mike Inouye	06e3ac4415	Fix bug when setting Verific runtime string flags. ... Signed-off-by: Mike Inouye <mikeinouye@google.com>	2024-11-12 18:46:26 +00:00
Akash Levy	83234d24f7	Switch from Synopsys register naming to preserve	2024-11-11 17:06:56 -08:00
Akash Levy	894c9816d3	Improve naming: big fix	2024-11-11 17:06:11 -08:00
Miodrag Milanovic	df391f5816	verific: fix blackbox regression and add test case	2024-11-08 14:57:04 +01:00
Alain Dargelas	615f523ef4	pass no_split_complex_ports to hierarchy command	2024-10-29 13:37:03 -07:00
Akash Levy	5e606722e3	Get autoidx reset working	2024-10-28 16:30:47 -07:00
Akash Levy	038c562493	VHDL support fix	2024-10-25 11:32:52 -07:00
Akash Levy	8e667e2e9f	Add documentation for VHDL library directory	2024-10-23 23:53:21 -07:00
Akash Levy	17c8567b02	Really tiny fixes	2024-10-23 22:03:00 -07:00
Akash Levy	3d127dff4a	Add set VHDL default library path	2024-10-21 01:22:56 -07:00
Akash Levy	c94eac14b9	Remove GHDL and add mixed SV-VHDL support	2024-10-20 23:29:33 -07:00
Akash Levy	e2659247fc	Verific UPF eval working	2024-10-17 04:40:38 -07:00
Akash Levy	469f5a707a	Merge branch 'YosysHQ:main' into main	2024-10-14 11:21:54 -07:00