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Ignore unused modules

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This commit is contained in:
Alain Dargelas 2024-12-03 13:00:14 -08:00
parent fe684f5fd2
commit 350b04daa3
1 changed files with 1 additions and 0 deletions
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frontends/verific/verific.cc
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@ -3544,6 +3544,7 @@ struct VerificPass : public Pass {
// RuntimeFlags::SetVar("veri_break_loops", 0); // SILIMATE: add to avoid breaking loops
RuntimeFlags::SetVar("veri_optimize_wide_selector", 1); // SILIMATE: add to optimize wide selector
RuntimeFlags::SetVar("veri_ignore_assertion_statements", 1); // SILIMATE: add to ignore SVA/asserts
RuntimeFlags::SetVar("verilog_ignore_unnecessary_modules_in_v_files", 1); // SILIMATE: add to ignore unnecessary modules
#endif
#ifdef VERIFIC_VHDL_SUPPORT
RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);