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Merge pull request #30 from alaindargelas/macro_power

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Simulation information for macro power
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Akash Levy 2024-12-04 10:01:04 -08:00 • committed by GitHub
commit 7847b1b2eb
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3 changed files with 8 additions and 1 deletions
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1
frontends/verific/verific.cc
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@ -3546,6 +3546,7 @@ struct VerificPass : public Pass {
// RuntimeFlags::SetVar("veri_break_loops", 0); // SILIMATE: add to avoid breaking loops
RuntimeFlags::SetVar("veri_optimize_wide_selector", 1); // SILIMATE: add to optimize wide selector
RuntimeFlags::SetVar("veri_ignore_assertion_statements", 1); // SILIMATE: add to ignore SVA/asserts
RuntimeFlags::SetVar("verilog_ignore_unnecessary_modules_in_v_files", 1); // SILIMATE: add to ignore unnecessary modules
#endif
#ifdef VERIFIC_VHDL_SUPPORT
RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);

2
passes/cmds/activity.cc
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@ -178,7 +178,7 @@ struct ActivityPropPass : public Pass {
ActivityProp worker(module);
totalNbBitsWithActivity += worker.getNbBitsWithActivity();
}
log("Collected %d bits with activity", totalNbBitsWithActivity);
log("Collected %d bits with activity\n", totalNbBitsWithActivity);
log_flush();
}
} ActivityPropPass;

6
passes/sat/sim.cc
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@ -28,6 +28,8 @@
#include "kernel/fmt.h"
#include <ctime>
#include <sstream>
#include <iomanip>
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
@ -2541,6 +2543,10 @@ struct AnnotateActivity : public OutputWriter {
double clk_period = real_timescale * (double)max_time / (clktoggleCounts[0] / 2.0);
double frequency = 1.0 / clk_period;
worker->top->module->set_string_attribute("$FREQUENCY", std::to_string(frequency));
worker->top->module->set_string_attribute("$DURATION", std::to_string(max_time));
std::stringstream ss;
ss << std::setprecision(4) << real_timescale;
worker->top->module->set_string_attribute("$TIMESCALE", ss.str());
if (debug) {
std::cout << "Clock toggle count: " << clktoggleCounts[0] << "\n";
std::cout << "Max time: " << max_time << "\n";