810 commits

Author	SHA1	Message	Date
Clifford Wolf	aa7a3ed83f	Fixed proc_{self,share}_dirname error handling	2014-08-17 02:25:59 +02:00
Clifford Wolf	f3326a6421	Improved sig.remove2() performance	2014-08-17 02:16:56 +02:00
Clifford Wolf	9bacc0b54c	Added stackmap<> container	2014-08-17 00:56:47 +02:00
Clifford Wolf	410d043dd8	Renamed toposort.h to utils.h	2014-08-17 00:55:35 +02:00
Clifford Wolf	7f734ecc09	Added module->uniquify()	2014-08-16 23:50:36 +02:00
Clifford Wolf	47c2637a96	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_	2014-08-16 18:29:39 +02:00
Clifford Wolf	56a30cf42c	Added CellTypes::cell_evaluable()	2014-08-16 16:17:07 +02:00
Clifford Wolf	dbdf89c705	Added log_spacer()	2014-08-16 15:34:00 +02:00
Clifford Wolf	b64b38eea2	Renamed $lut ports to follow A-Y naming scheme	2014-08-15 14:18:40 +02:00
Clifford Wolf	f092b50148	Renamed $_INV_ cell type to $_NOT_	2014-08-15 14:11:40 +02:00
Clifford Wolf	ca87116449	More idstring sort_by_* helpers and fixed tpl ordering in techmap	2014-08-15 02:40:46 +02:00
Clifford Wolf	8ff71b5ae5	Added Frontend "+/" filename syntax for files from proc_share_dir	2014-08-15 02:08:02 +02:00
Clifford Wolf	978a933b6a	Added RTLIL::SigSpec::to_sigbit_map()	2014-08-14 23:14:47 +02:00
Clifford Wolf	2f44d8ccf8	Added sig.{replace,remove,extract} variants for std::{map,set} pattern	2014-08-14 22:32:18 +02:00
Clifford Wolf	1bf7a18fec	Added module->ports	2014-08-14 16:22:52 +02:00
Clifford Wolf	746aac540b	Refactoring of CellType class	2014-08-14 15:46:51 +02:00
Clifford Wolf	13f2f36884	RIP $safe_pmux	2014-08-14 11:39:46 +02:00
Clifford Wolf	e5ac8fdf2b	Fixed SigBit(RTLIL::Wire *wire) constructor	2014-08-12 15:39:48 +02:00
Clifford Wolf	5215723c64	Another build fix by americanrouter (via reddit)	2014-08-11 15:55:41 +02:00
Clifford Wolf	0b8b8d41eb	Fixed build with gcc-4.6	2014-08-07 22:37:01 +02:00
Clifford Wolf	523df73145	Added support for truncating of wires to wreduce pass	2014-08-05 14:47:03 +02:00
Clifford Wolf	ebbbe7fc83	Added RTLIL::IdString::in(...)	2014-08-04 15:40:07 +02:00
Clifford Wolf	653edd7a2f	Added query() API to ModIndex	2014-08-03 15:00:38 +02:00
Clifford Wolf	75423169c5	Added ID() macro for static IdStrings	2014-08-03 14:59:13 +02:00
Clifford Wolf	bc947d4c7b	Fixed a va_list corruption in logv_error()	2014-08-02 21:54:30 +02:00
Clifford Wolf	b6acbc82e6	Bugfix in "techmap -extern"	2014-08-02 20:54:30 +02:00
Clifford Wolf	8e7361f128	Removed at() method from RTLIL::IdString	2014-08-02 19:08:02 +02:00
Clifford Wolf	04727c7e0f	No implicit conversion from IdString to anything else	2014-08-02 18:58:40 +02:00
Clifford Wolf	768eb846c4	More bugfixes related to new RTLIL::IdString	2014-08-02 18:14:21 +02:00
Clifford Wolf	08392aad8f	Limit size of log_signal buffer to 100 elements	2014-08-02 15:52:21 +02:00
Clifford Wolf	e590ffc84d	Improvements in new RTLIL::IdString implementation	2014-08-02 15:44:10 +02:00
Clifford Wolf	60f3dc9923	Implemented new reference counting RTLIL::IdString	2014-08-02 15:11:35 +02:00
Clifford Wolf	97ad0623df	Fixed memory corruption related to id2cstr()	2014-08-02 13:34:07 +02:00
Clifford Wolf	b9bd22b8c8	More cleanups related to RTLIL::IdString usage	2014-08-02 13:19:57 +02:00
Clifford Wolf	14412e6c95	Preparations for RTLIL::IdString redesign: cleanup of existing code	2014-08-02 00:45:25 +02:00
Clifford Wolf	75ffd1643c	Added logfile hash to statistics footer	2014-08-01 19:43:28 +02:00
Clifford Wolf	1e224506be	Added per-pass cpu usage statistics	2014-08-01 18:42:10 +02:00
Clifford Wolf	d13eb7e099	Added ModIndex helper class, some changes to RTLIL::Monitor	2014-08-01 17:14:32 +02:00
Clifford Wolf	97a17d39e2	Packed SigBit::data and SigBit::offset in a union	2014-08-01 15:25:42 +02:00
Clifford Wolf	32a1cc3efd	Renamed modwalker.h to modtools.h	2014-07-31 23:30:18 +02:00
Clifford Wolf	cdae8abe16	Renamed port access function on RTLIL::Cell, added param access functions	2014-07-31 16:38:54 +02:00
Clifford Wolf	b5a9e51b96	Added "trace" command	2014-07-31 15:02:16 +02:00
Clifford Wolf	cd9407404a	Added RTLIL::Monitor	2014-07-31 14:45:14 +02:00
Clifford Wolf	e6d33513a5	Added module->design and cell->module, wire->module pointers	2014-07-31 14:11:39 +02:00
Clifford Wolf	1cb25c05b3	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00
Clifford Wolf	6166c76831	Added "yosys -A"	2014-07-31 01:05:27 +02:00
Clifford Wolf	e5c245df9d	Added "yosys -Q"	2014-07-31 00:53:21 +02:00
Clifford Wolf	2541489105	Added techmap CONSTMAP feature	2014-07-30 22:04:30 +02:00
Clifford Wolf	6400ae3648	Added write_file command	2014-07-30 19:59:29 +02:00
Clifford Wolf	3f0a5746ef	Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models	2014-07-30 18:37:17 +02:00