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Renamed port access function on RTLIL::Cell, added param access functions

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This commit is contained in:
Clifford Wolf 2014-07-31 16:38:54 +02:00
parent b5a9e51b96
commit cdae8abe16
46 changed files with 1086 additions and 1059 deletions
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16
kernel/consteval.h
View file

@ -87,22 +87,22 @@ struct ConstEval
{
RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;
log_assert(cell->has("\\Y"));
sig_y = values_map(assign_map(cell->get("\\Y")));
log_assert(cell->hasPort("\\Y"));
sig_y = values_map(assign_map(cell->getPort("\\Y")));
if (sig_y.is_fully_const())
return true;
if (cell->has("\\S")) {
sig_s = cell->get("\\S");
if (cell->hasPort("\\S")) {
sig_s = cell->getPort("\\S");
if (!eval(sig_s, undef, cell))
return false;
}
if (cell->has("\\A"))
sig_a = cell->get("\\A");
if (cell->hasPort("\\A"))
sig_a = cell->getPort("\\A");
if (cell->has("\\B"))
sig_b = cell->get("\\B");
if (cell->hasPort("\\B"))
sig_b = cell->getPort("\\B");
if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux" || cell->type == "$_MUX_")
{

184
kernel/rtlil.cc
View file

@ -447,9 +447,9 @@ namespace {
void port(const char *name, int width)
{
if (!cell->has(name))
if (!cell->hasPort(name))
error(__LINE__);
if (cell->get(name).size() != width)
if (cell->getPort(name).size() != width)
error(__LINE__);
expected_ports.insert(name);
}
@ -478,9 +478,9 @@ namespace {
for (const char *p = ports; *p; p++) {
char portname[3] = { '\\', *p, 0 };
if (!cell->has(portname))
if (!cell->hasPort(portname))
error(__LINE__);
if (cell->get(portname).size() != 1)
if (cell->getPort(portname).size() != 1)
error(__LINE__);
}
@ -1001,7 +1001,7 @@ namespace {
#if 0
void RTLIL::Module::remove(RTLIL::Wire *wire)
{
std::set<RTLIL::Wire*> wires_;
std::setPort<RTLIL::Wire*> wires_;
wires_.insert(wire);
remove(wires_);
}
@ -1167,8 +1167,8 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
cell->parameters["\\A_SIGNED"] = is_signed; \
cell->parameters["\\A_WIDTH"] = sig_a.size(); \
cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
cell->set("\\A", sig_a); \
cell->set("\\Y", sig_y); \
cell->setPort("\\A", sig_a); \
cell->setPort("\\Y", sig_y); \
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
@ -1196,9 +1196,9 @@ DEF_METHOD(LogicNot, 1, "$logic_not")
cell->parameters["\\A_WIDTH"] = sig_a.size(); \
cell->parameters["\\B_WIDTH"] = sig_b.size(); \
cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
cell->set("\\A", sig_a); \
cell->set("\\B", sig_b); \
cell->set("\\Y", sig_y); \
cell->setPort("\\A", sig_a); \
cell->setPort("\\B", sig_b); \
cell->setPort("\\Y", sig_y); \
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
@ -1239,10 +1239,10 @@ DEF_METHOD(LogicOr, 1, "$logic_or")
cell->parameters["\\WIDTH"] = sig_a.size(); \
cell->parameters["\\WIDTH"] = sig_b.size(); \
if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
cell->set("\\A", sig_a); \
cell->set("\\B", sig_b); \
cell->set("\\S", sig_s); \
cell->set("\\Y", sig_y); \
cell->setPort("\\A", sig_a); \
cell->setPort("\\B", sig_b); \
cell->setPort("\\S", sig_s); \
cell->setPort("\\Y", sig_y); \
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
@ -1258,8 +1258,8 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1)
#define DEF_METHOD_2(_func, _type, _P1, _P2) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
RTLIL::Cell *cell = addCell(name, _type); \
cell->set("\\" #_P1, sig1); \
cell->set("\\" #_P2, sig2); \
cell->setPort("\\" #_P1, sig1); \
cell->setPort("\\" #_P2, sig2); \
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1) { \
@ -1270,9 +1270,9 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1)
#define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
RTLIL::Cell *cell = addCell(name, _type); \
cell->set("\\" #_P1, sig1); \
cell->set("\\" #_P2, sig2); \
cell->set("\\" #_P3, sig3); \
cell->setPort("\\" #_P1, sig1); \
cell->setPort("\\" #_P2, sig2); \
cell->setPort("\\" #_P3, sig3); \
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
@ -1283,10 +1283,10 @@ DEF_METHOD(SafePmux, "$safe_pmux", 1)
#define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3, RTLIL::SigSpec sig4) { \
RTLIL::Cell *cell = addCell(name, _type); \
cell->set("\\" #_P1, sig1); \
cell->set("\\" #_P2, sig2); \
cell->set("\\" #_P3, sig3); \
cell->set("\\" #_P4, sig4); \
cell->setPort("\\" #_P1, sig1); \
cell->setPort("\\" #_P2, sig2); \
cell->setPort("\\" #_P3, sig3); \
cell->setPort("\\" #_P4, sig4); \
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
@ -1311,9 +1311,9 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, R
cell->parameters["\\A_WIDTH"] = sig_a.size();
cell->parameters["\\B_WIDTH"] = sig_b.size();
cell->parameters["\\Y_WIDTH"] = sig_y.size();
cell->set("\\A", sig_a);
cell->set("\\B", sig_b);
cell->set("\\Y", sig_y);
cell->setPort("\\A", sig_a);
cell->setPort("\\B", sig_b);
cell->setPort("\\Y", sig_y);
return cell;
}
@ -1323,8 +1323,8 @@ RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a,
cell->parameters["\\A_WIDTH"] = sig_a.size();
cell->parameters["\\Y_WIDTH"] = sig_y.size();
cell->parameters["\\OFFSET"] = offset;
cell->set("\\A", sig_a);
cell->set("\\Y", sig_y);
cell->setPort("\\A", sig_a);
cell->setPort("\\Y", sig_y);
return cell;
}
@ -1333,9 +1333,9 @@ RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a
RTLIL::Cell *cell = addCell(name, "$concat");
cell->parameters["\\A_WIDTH"] = sig_a.size();
cell->parameters["\\B_WIDTH"] = sig_b.size();
cell->set("\\A", sig_a);
cell->set("\\B", sig_b);
cell->set("\\Y", sig_y);
cell->setPort("\\A", sig_a);
cell->setPort("\\B", sig_b);
cell->setPort("\\Y", sig_y);
return cell;
}
@ -1344,16 +1344,16 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, R
RTLIL::Cell *cell = addCell(name, "$lut");
cell->parameters["\\LUT"] = lut;
cell->parameters["\\WIDTH"] = sig_i.size();
cell->set("\\I", sig_i);
cell->set("\\O", sig_o);
cell->setPort("\\I", sig_i);
cell->setPort("\\O", sig_o);
return cell;
}
RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
{
RTLIL::Cell *cell = addCell(name, "$assert");
cell->set("\\A", sig_a);
cell->set("\\EN", sig_en);
cell->setPort("\\A", sig_a);
cell->setPort("\\EN", sig_en);
return cell;
}
@ -1363,9 +1363,9 @@ RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set,
cell->parameters["\\SET_POLARITY"] = set_polarity;
cell->parameters["\\CLR_POLARITY"] = clr_polarity;
cell->parameters["\\WIDTH"] = sig_q.size();
cell->set("\\SET", sig_set);
cell->set("\\CLR", sig_clr);
cell->set("\\Q", sig_q);
cell->setPort("\\SET", sig_set);
cell->setPort("\\CLR", sig_clr);
cell->setPort("\\Q", sig_q);
return cell;
}
@ -1374,9 +1374,9 @@ RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk,
RTLIL::Cell *cell = addCell(name, "$dff");
cell->parameters["\\CLK_POLARITY"] = clk_polarity;
cell->parameters["\\WIDTH"] = sig_q.size();
cell->set("\\CLK", sig_clk);
cell->set("\\D", sig_d);
cell->set("\\Q", sig_q);
cell->setPort("\\CLK", sig_clk);
cell->setPort("\\D", sig_d);
cell->setPort("\\Q", sig_q);
return cell;
}
@ -1388,11 +1388,11 @@ RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_cl
cell->parameters["\\SET_POLARITY"] = set_polarity;
cell->parameters["\\CLR_POLARITY"] = clr_polarity;
cell->parameters["\\WIDTH"] = sig_q.size();
cell->set("\\CLK", sig_clk);
cell->set("\\SET", sig_set);
cell->set("\\CLR", sig_clr);
cell->set("\\D", sig_d);
cell->set("\\Q", sig_q);
cell->setPort("\\CLK", sig_clk);
cell->setPort("\\SET", sig_set);
cell->setPort("\\CLR", sig_clr);
cell->setPort("\\D", sig_d);
cell->setPort("\\Q", sig_q);
return cell;
}
@ -1404,10 +1404,10 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk
cell->parameters["\\ARST_POLARITY"] = arst_polarity;
cell->parameters["\\ARST_VALUE"] = arst_value;
cell->parameters["\\WIDTH"] = sig_q.size();
cell->set("\\CLK", sig_clk);
cell->set("\\ARST", sig_arst);
cell->set("\\D", sig_d);
cell->set("\\Q", sig_q);
cell->setPort("\\CLK", sig_clk);
cell->setPort("\\ARST", sig_arst);
cell->setPort("\\D", sig_d);
cell->setPort("\\Q", sig_q);
return cell;
}
@ -1416,9 +1416,9 @@ RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, RTLIL::SigSpec sig_e
RTLIL::Cell *cell = addCell(name, "$dlatch");
cell->parameters["\\EN_POLARITY"] = en_polarity;
cell->parameters["\\WIDTH"] = sig_q.size();
cell->set("\\EN", sig_en);
cell->set("\\D", sig_d);
cell->set("\\Q", sig_q);
cell->setPort("\\EN", sig_en);
cell->setPort("\\D", sig_d);
cell->setPort("\\Q", sig_q);
return cell;
}
@ -1430,20 +1430,20 @@ RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig
cell->parameters["\\SET_POLARITY"] = set_polarity;
cell->parameters["\\CLR_POLARITY"] = clr_polarity;
cell->parameters["\\WIDTH"] = sig_q.size();
cell->set("\\EN", sig_en);
cell->set("\\SET", sig_set);
cell->set("\\CLR", sig_clr);
cell->set("\\D", sig_d);
cell->set("\\Q", sig_q);
cell->setPort("\\EN", sig_en);
cell->setPort("\\SET", sig_set);
cell->setPort("\\CLR", sig_clr);
cell->setPort("\\D", sig_d);
cell->setPort("\\Q", sig_q);
return cell;
}
RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
{
RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
cell->set("\\C", sig_clk);
cell->set("\\D", sig_d);
cell->set("\\Q", sig_q);
cell->setPort("\\C", sig_clk);
cell->setPort("\\D", sig_d);
cell->setPort("\\Q", sig_q);
return cell;
}
@ -1451,11 +1451,11 @@ RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec si
RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
{
RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
cell->set("\\C", sig_clk);
cell->set("\\S", sig_set);
cell->set("\\R", sig_clr);
cell->set("\\D", sig_d);
cell->set("\\Q", sig_q);
cell->setPort("\\C", sig_clk);
cell->setPort("\\S", sig_set);
cell->setPort("\\R", sig_clr);
cell->setPort("\\D", sig_d);
cell->setPort("\\Q", sig_q);
return cell;
}
@ -1463,19 +1463,19 @@ RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, RTLIL::SigSpec sig
bool arst_value, bool clk_polarity, bool arst_polarity)
{
RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
cell->set("\\C", sig_clk);
cell->set("\\R", sig_arst);
cell->set("\\D", sig_d);
cell->set("\\Q", sig_q);
cell->setPort("\\C", sig_clk);
cell->setPort("\\R", sig_arst);
cell->setPort("\\D", sig_d);
cell->setPort("\\Q", sig_q);
return cell;
}
RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity)
{
RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
cell->set("\\E", sig_en);
cell->set("\\D", sig_d);
cell->set("\\Q", sig_q);
cell->setPort("\\E", sig_en);
cell->setPort("\\D", sig_d);
cell->setPort("\\Q", sig_q);
return cell;
}
@ -1483,11 +1483,11 @@ RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, RTLIL::SigSpec
RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool en_polarity, bool set_polarity, bool clr_polarity)
{
RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
cell->set("\\E", sig_en);
cell->set("\\S", sig_set);
cell->set("\\R", sig_clr);
cell->set("\\D", sig_d);
cell->set("\\Q", sig_q);
cell->setPort("\\E", sig_en);
cell->setPort("\\S", sig_set);
cell->setPort("\\R", sig_clr);
cell->setPort("\\D", sig_d);
cell->setPort("\\Q", sig_q);
return cell;
}
@ -1509,12 +1509,12 @@ RTLIL::Memory::Memory()
size = 0;
}
bool RTLIL::Cell::has(RTLIL::IdString portname) const
bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
{
return connections_.count(portname) != 0;
}
void RTLIL::Cell::unset(RTLIL::IdString portname)
void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
{
std::pair<RTLIL::IdString, RTLIL::SigSpec> new_conn(portname, RTLIL::SigSpec());
@ -1528,7 +1528,7 @@ void RTLIL::Cell::unset(RTLIL::IdString portname)
connections_.erase(portname);
}
void RTLIL::Cell::set(RTLIL::IdString portname, RTLIL::SigSpec signal)
void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
{
std::pair<RTLIL::IdString, RTLIL::SigSpec> new_conn(portname, signal);
@ -1542,7 +1542,7 @@ void RTLIL::Cell::set(RTLIL::IdString portname, RTLIL::SigSpec signal)
connections_[portname] = signal;
}
const RTLIL::SigSpec &RTLIL::Cell::get(RTLIL::IdString portname) const
const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
{
return connections_.at(portname);
}
@ -1552,6 +1552,26 @@ const std::map<RTLIL::IdString, RTLIL::SigSpec> &RTLIL::Cell::connections() cons
return connections_;
}
bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
{
return parameters.count(paramname);
}
void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
{
parameters.erase(paramname);
}
void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
{
parameters[paramname] = value;
}
const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
{
return parameters.at(paramname);
}
void RTLIL::Cell::check()
{
#ifndef NDEBUG

15
kernel/rtlil.h
View file

@ -331,6 +331,7 @@ struct RTLIL::Selection
struct RTLIL::Monitor
{
virtual ~Monitor() { }
virtual void notify_module_add(RTLIL::Module*) { }
virtual void notify_module_del(RTLIL::Module*) { }
virtual void notify_cell_connect(RTLIL::Cell*, const std::pair<RTLIL::IdString, RTLIL::SigSpec>&) { }
@ -663,12 +664,18 @@ public:
RTLIL_ATTRIBUTE_MEMBERS
// access cell ports
bool has(RTLIL::IdString portname) const;
void unset(RTLIL::IdString portname);
void set(RTLIL::IdString portname, RTLIL::SigSpec signal);
const RTLIL::SigSpec &get(RTLIL::IdString portname) const;
bool hasPort(RTLIL::IdString portname) const;
void unsetPort(RTLIL::IdString portname);
void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal);
const RTLIL::SigSpec &getPort(RTLIL::IdString portname) const;
const std::map<RTLIL::IdString, RTLIL::SigSpec> &connections() const;
// access cell parameters
bool hasParam(RTLIL::IdString portname) const;
void unsetParam(RTLIL::IdString portname);
void setParam(RTLIL::IdString portname, RTLIL::Const value);
const RTLIL::Const &getParam(RTLIL::IdString portname) const;
void check();
void fixup_parameters(bool set_a_signed = false, bool set_b_signed = false);

170
kernel/satgen.h
View file

@ -182,9 +182,9 @@ struct SatGen
if (model_undef && (cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || is_arith_compare))
{
std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
if (is_arith_compare)
extendSignalWidth(undef_a, undef_b, cell, true);
else
@ -195,7 +195,7 @@ struct SatGen
int undef_y_bit = ez->OR(undef_any_a, undef_any_b);
if (cell->type == "$div" || cell->type == "$mod") {
std::vector<int> b = importSigSpec(cell->get("\\B"), timestep);
std::vector<int> b = importSigSpec(cell->getPort("\\B"), timestep);
undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b)));
}
@ -215,9 +215,9 @@ struct SatGen
cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" ||
cell->type == "$add" || cell->type == "$sub")
{
std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
extendSignalWidth(a, b, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -237,9 +237,9 @@ struct SatGen
if (model_undef && !arith_undef_handled)
{
std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
extendSignalWidth(undef_a, undef_b, undef_y, cell, false);
if (cell->type == "$and" || cell->type == "$_AND_") {
@ -265,7 +265,7 @@ struct SatGen
}
else if (model_undef)
{
std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
undefGating(y, yy, undef_y);
}
return true;
@ -273,16 +273,16 @@ struct SatGen
if (cell->type == "$_INV_" || cell->type == "$not")
{
std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
extendSignalWidthUnary(a, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
ez->assume(ez->vec_eq(ez->vec_not(a), yy));
if (model_undef) {
std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
extendSignalWidthUnary(undef_a, undef_y, cell, true);
ez->assume(ez->vec_eq(undef_a, undef_y));
undefGating(y, yy, undef_y);
@ -292,20 +292,20 @@ struct SatGen
if (cell->type == "$_MUX_" || cell->type == "$mux")
{
std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
std::vector<int> s = importDefSigSpec(cell->get("\\S"), timestep);
std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort("\\S"), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
ez->assume(ez->vec_eq(ez->vec_ite(s.at(0), b, a), yy));
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
std::vector<int> undef_s = importUndefSigSpec(cell->get("\\S"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
std::vector<int> undef_s = importUndefSigSpec(cell->getPort("\\S"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
std::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));
std::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));
@ -318,10 +318,10 @@ struct SatGen
if (cell->type == "$pmux" || cell->type == "$safe_pmux")
{
std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
std::vector<int> s = importDefSigSpec(cell->get("\\S"), timestep);
std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort("\\S"), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -336,10 +336,10 @@ struct SatGen
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
std::vector<int> undef_s = importUndefSigSpec(cell->get("\\S"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
std::vector<int> undef_s = importUndefSigSpec(cell->getPort("\\S"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
int maybe_one_hot = ez->FALSE;
int maybe_many_hot = ez->FALSE;
@ -387,8 +387,8 @@ struct SatGen
if (cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg")
{
std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
extendSignalWidthUnary(a, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -402,8 +402,8 @@ struct SatGen
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
extendSignalWidthUnary(undef_a, undef_y, cell, cell->type != "$bu0");
if (cell->type == "$pos" || cell->type == "$bu0") {
@ -422,8 +422,8 @@ struct SatGen
if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_xor" ||
cell->type == "$reduce_xnor" || cell->type == "$reduce_bool" || cell->type == "$logic_not")
{
std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -442,8 +442,8 @@ struct SatGen
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
int aX = ez->expression(ezSAT::OpOr, undef_a);
if (cell->type == "$reduce_and") {
@ -469,12 +469,12 @@ struct SatGen
if (cell->type == "$logic_and" || cell->type == "$logic_or")
{
std::vector<int> vec_a = importDefSigSpec(cell->get("\\A"), timestep);
std::vector<int> vec_b = importDefSigSpec(cell->get("\\B"), timestep);
std::vector<int> vec_a = importDefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> vec_b = importDefSigSpec(cell->getPort("\\B"), timestep);
int a = ez->expression(ez->OpOr, vec_a);
int b = ez->expression(ez->OpOr, vec_b);
std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -487,9 +487,9 @@ struct SatGen
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
int a0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_a), ez->expression(ezSAT::OpOr, undef_a)));
int b0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_b), ez->expression(ezSAT::OpOr, undef_b)));
@ -516,16 +516,16 @@ struct SatGen
if (cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt")
{
bool is_signed = cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool();
std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
extendSignalWidth(a, b, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
if (model_undef && (cell->type == "$eqx" || cell->type == "$nex")) {
std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
extendSignalWidth(undef_a, undef_b, cell, true);
a = ez->vec_or(a, undef_a);
b = ez->vec_or(b, undef_b);
@ -548,9 +548,9 @@ struct SatGen
if (model_undef && (cell->type == "$eqx" || cell->type == "$nex"))
{
std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
extendSignalWidth(undef_a, undef_b, cell, true);
if (cell->type == "$eqx")
@ -565,9 +565,9 @@ struct SatGen
}
else if (model_undef && (cell->type == "$eq" || cell->type == "$ne"))
{
std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
extendSignalWidth(undef_a, undef_b, cell, true);
int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
@ -589,7 +589,7 @@ struct SatGen
else
{
if (model_undef) {
std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
undefGating(y, yy, undef_y);
}
log_assert(!model_undef || arith_undef_handled);
@ -599,9 +599,9 @@ struct SatGen
if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" || cell->type == "$shift" || cell->type == "$shiftx")
{
std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
int extend_bit = ez->FALSE;
@ -632,9 +632,9 @@ struct SatGen
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->get("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->get("\\B"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort("\\B"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
std::vector<int> undef_a_shifted;
if (cell->type != "$shift" && cell->type != "$shiftx" && cell->parameters["\\A_SIGNED"].as_bool())
@ -670,9 +670,9 @@ struct SatGen
if (cell->type == "$mul")
{
std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
extendSignalWidth(a, b, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -689,7 +689,7 @@ struct SatGen
if (model_undef) {
log_assert(arith_undef_handled);
std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
undefGating(y, yy, undef_y);
}
return true;
@ -697,9 +697,9 @@ struct SatGen
if (cell->type == "$div" || cell->type == "$mod")
{
std::vector<int> a = importDefSigSpec(cell->get("\\A"), timestep);
std::vector<int> b = importDefSigSpec(cell->get("\\B"), timestep);
std::vector<int> y = importDefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort("\\Y"), timestep);
extendSignalWidth(a, b, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -753,11 +753,11 @@ struct SatGen
only_first_one.at(0) = ez->TRUE;
div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones);
} else {
div_zero_result.insert(div_zero_result.end(), cell->get("\\A").size(), ez->TRUE);
div_zero_result.insert(div_zero_result.end(), cell->getPort("\\A").size(), ez->TRUE);
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->FALSE);
}
} else {
int copy_a_bits = std::min(cell->get("\\A").size(), cell->get("\\B").size());
int copy_a_bits = std::min(cell->getPort("\\A").size(), cell->getPort("\\B").size());
div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
if (cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool())
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());
@ -769,7 +769,7 @@ struct SatGen
if (model_undef) {
log_assert(arith_undef_handled);
std::vector<int> undef_y = importUndefSigSpec(cell->get("\\Y"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
undefGating(y, yy, undef_y);
}
return true;
@ -777,17 +777,17 @@ struct SatGen
if (cell->type == "$slice")
{
RTLIL::SigSpec a = cell->get("\\A");
RTLIL::SigSpec y = cell->get("\\Y");
RTLIL::SigSpec a = cell->getPort("\\A");
RTLIL::SigSpec y = cell->getPort("\\Y");
ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.size()), y, timestep));
return true;
}
if (cell->type == "$concat")
{
RTLIL::SigSpec a = cell->get("\\A");
RTLIL::SigSpec b = cell->get("\\B");
RTLIL::SigSpec y = cell->get("\\Y");
RTLIL::SigSpec a = cell->getPort("\\A");
RTLIL::SigSpec b = cell->getPort("\\B");
RTLIL::SigSpec y = cell->getPort("\\Y");
RTLIL::SigSpec ab = a;
ab.append(b);
@ -800,20 +800,20 @@ struct SatGen
{
if (timestep == 1)
{
initial_state.add((*sigmap)(cell->get("\\Q")));
initial_state.add((*sigmap)(cell->getPort("\\Q")));
}
else
{
std::vector<int> d = importDefSigSpec(cell->get("\\D"), timestep-1);
std::vector<int> q = importDefSigSpec(cell->get("\\Q"), timestep);
std::vector<int> d = importDefSigSpec(cell->getPort("\\D"), timestep-1);
std::vector<int> q = importDefSigSpec(cell->getPort("\\Q"), timestep);
std::vector<int> qq = model_undef ? ez->vec_var(q.size()) : q;
ez->assume(ez->vec_eq(d, qq));
if (model_undef)
{
std::vector<int> undef_d = importUndefSigSpec(cell->get("\\D"), timestep-1);
std::vector<int> undef_q = importUndefSigSpec(cell->get("\\Q"), timestep);
std::vector<int> undef_d = importUndefSigSpec(cell->getPort("\\D"), timestep-1);
std::vector<int> undef_q = importUndefSigSpec(cell->getPort("\\Q"), timestep);
ez->assume(ez->vec_eq(undef_d, undef_q));
undefGating(q, qq, undef_q);
@ -825,8 +825,8 @@ struct SatGen
if (cell->type == "$assert")
{
std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
asserts_a[pf].append((*sigmap)(cell->get("\\A")));
asserts_en[pf].append((*sigmap)(cell->get("\\EN")));
asserts_a[pf].append((*sigmap)(cell->getPort("\\A")));
asserts_en[pf].append((*sigmap)(cell->getPort("\\EN")));
return true;
}