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Added module->uniquify()
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parent
f82c978e08
commit
7f734ecc09
5 changed files with 29 additions and 15 deletions
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@ -1108,6 +1108,28 @@ void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
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cells_[c2->name] = c2;
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}
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RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
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{
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int index = 0;
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return uniquify(name, index);
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}
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RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
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{
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if (index == 0) {
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if (count_id(name) == 0)
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return name;
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index++;
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}
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while (1) {
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RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
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if (count_id(new_name) == 0)
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return new_name;
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index++;
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}
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}
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static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
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{
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if (a->port_id && !b->port_id)
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@ -625,6 +625,9 @@ public:
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void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);
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void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);
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RTLIL::IdString uniquify(RTLIL::IdString name);
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RTLIL::IdString uniquify(RTLIL::IdString name, int &index);
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RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
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RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
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