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Added support for truncating of wires to wreduce pass

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This commit is contained in:
Clifford Wolf 2014-08-05 14:47:03 +02:00
parent d3b1a29708
commit 523df73145
4 changed files with 93 additions and 12 deletions
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24
kernel/modtools.h
View file

@ -59,14 +59,20 @@ struct ModIndex : public RTLIL::Monitor
void port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
{
for (int i = 0; i < SIZE(sig); i++)
database[sigmap(sig[i])].ports.insert(PortInfo(cell, port, i));
for (int i = 0; i < SIZE(sig); i++) {
RTLIL::SigBit bit = sigmap(sig[i]);
if (bit.wire)
database[bit].ports.insert(PortInfo(cell, port, i));
}
}
void port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
{
for (int i = 0; i < SIZE(sig); i++)
database[sigmap(sig[i])].ports.erase(PortInfo(cell, port, i));
for (int i = 0; i < SIZE(sig); i++) {
RTLIL::SigBit bit = sigmap(sig[i]);
if (bit.wire)
database[bit].ports.erase(PortInfo(cell, port, i));
}
}
const SigBitInfo &info(RTLIL::SigBit bit)
@ -83,10 +89,11 @@ struct ModIndex : public RTLIL::Monitor
for (auto wire : module->wires())
if (wire->port_input || wire->port_output)
for (int i = 0; i < SIZE(wire); i++) {
if (wire->port_input)
database[sigmap(RTLIL::SigBit(wire, i))].is_input = true;
if (wire->port_output)
database[sigmap(RTLIL::SigBit(wire, i))].is_output = true;
RTLIL::SigBit bit = sigmap(RTLIL::SigBit(wire, i));
if (bit.wire && wire->port_input)
database[bit].is_input = true;
if (bit.wire && wire->port_output)
database[bit].is_output = true;
}
for (auto cell : module->cells())
for (auto &conn : cell->connections())
@ -137,6 +144,7 @@ struct ModIndex : public RTLIL::Monitor
{
if (auto_reload_module)
reload_module();
auto it = database.find(sigmap(bit));
if (it == database.end())
return nullptr;

30
kernel/rtlil.cc
View file

@ -1071,6 +1071,36 @@ void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
log_abort();
}
void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
{
log_assert(wires_[w1->name] == w1);
log_assert(wires_[w2->name] == w2);
log_assert(refcount_wires_ == 0);
wires_.erase(w1->name);
wires_.erase(w2->name);
std::swap(w1->name, w2->name);
wires_[w1->name] = w1;
wires_[w2->name] = w2;
}
void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
{
log_assert(cells_[c1->name] == c1);
log_assert(cells_[c2->name] == c2);
log_assert(refcount_cells_ == 0);
cells_.erase(c1->name);
cells_.erase(c2->name);
std::swap(c1->name, c2->name);
cells_[c1->name] = c1;
cells_[c2->name] = c2;
}
static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
{
if (a->port_id && !b->port_id)

7
kernel/rtlil.h
View file

@ -590,6 +590,10 @@ public:
std::vector<RTLIL::Wire*> selected_wires() const;
std::vector<RTLIL::Cell*> selected_cells() const;
template<typename T> bool selected(T *member) const {
return design->selected_member(name, member->name);
}
RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; }
RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; }
@ -604,6 +608,9 @@ public:
void rename(RTLIL::Cell *cell, RTLIL::IdString new_name);
void rename(RTLIL::IdString old_name, RTLIL::IdString new_name);
void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);
void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);
RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);