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Renamed $lut ports to follow A-Y naming scheme

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This commit is contained in:
Clifford Wolf 2014-08-15 14:18:40 +02:00
parent f092b50148
commit b64b38eea2
6 changed files with 38 additions and 39 deletions
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3
kernel/celltypes.h
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@ -88,7 +88,7 @@ struct CellTypes
std::vector<RTLIL::IdString> unary_ops = {
"$not", "$pos", "$bu0", "$neg",
"$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
"$logic_not", "$slice"
"$logic_not", "$slice", "$lut"
};
std::vector<RTLIL::IdString> binary_ops = {
@ -108,7 +108,6 @@ struct CellTypes
for (auto type : std::vector<RTLIL::IdString>({"$mux", "$pmux"}))
setup_type(type, {"\\A", "\\B", "\\S"}, {"\\Y"}, false);
setup_type("$lut", {"\\I"}, {"\\O"}, false);
setup_type("$assert", {"\\A", "\\EN"}, {}, false);
}

8
kernel/rtlil.cc
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@ -615,8 +615,8 @@ namespace {
if (cell->type == "$lut") {
param("\\LUT");
port("\\I", param("\\WIDTH"));
port("\\O", 1);
port("\\A", param("\\WIDTH"));
port("\\Y", 1);
check_expected();
return;
}
@ -1388,8 +1388,8 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, R
RTLIL::Cell *cell = addCell(name, "$lut");
cell->parameters["\\LUT"] = lut;
cell->parameters["\\WIDTH"] = sig_i.size();
cell->setPort("\\I", sig_i);
cell->setPort("\\O", sig_o);
cell->setPort("\\A", sig_i);
cell->setPort("\\Y", sig_o);
return cell;
}