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5130 commits

Author SHA1 Message Date
Akash Levy
dee059bee8 Fix minor Yosys issues 2025-09-30 12:05:36 -07:00
Akash Levy
c26f38faeb
Merge branch 'YosysHQ:main' into main 2025-09-30 11:14:33 -07:00
Emil J
7719beb4ae
Merge pull request #5349 from rocallahan/cleanup-hashops
Reduce hashops verbiage in `OptMergePass`
2025-09-30 19:34:44 +02:00
Akash Levy
16215b8786 Merge upstream 2025-09-29 20:58:56 -07:00
Akash Levy
313c7e4b95 Fix wreduce using queueing algorithm 2025-09-29 20:28:55 -07:00
Akash Levy
d36bc8231f Revert wreduce to initial state 2025-09-29 12:44:30 -07:00
Jannis Harder
47639f8a98
Merge pull request #5388 from jix/bufnorm-followup
Refactor and fixes to incremental bufNormalize + related changes
2025-09-29 15:15:29 +02:00
Jannis Harder
6a7372626a
Merge pull request #5389 from jix/sva_continue
verific: New `-sva-continue-on-error` import option
2025-09-29 15:07:54 +02:00
Emil J
87c1a868d3
Merge pull request #5384 from rocallahan/simplify-opt-merge-logic
Move `OptMerge` cell filtering logic to happen while building the cell vector
2025-09-29 15:03:01 +02:00
Akash Levy
ded986c510 Probably not fast but it works 2025-09-29 04:39:07 -07:00
Akash Levy
b2f2d6d6e3 Actually fix wreduce 2025-09-29 04:16:18 -07:00
Akash Levy
dfc8607a77 Fixups 2025-09-29 03:49:44 -07:00
Martin Povišer
a9318db2fa opt_hier: Adjust messages 2025-09-29 12:27:27 +02:00
Martin Povišer
ffe2f7a16d opt_hier: Fix two optimizations conflicting
Fix a conflict between the following two:

 * propagation of tied-together inputs in
 * propagation of unused inputs out
2025-09-29 12:27:27 +02:00
Akash Levy
fbc2b71ed4 Revert some stuff 2025-09-29 00:43:49 -07:00
Akash Levy
0b0c7bd19d Fix wreduce speed issue 2025-09-29 00:18:48 -07:00
Akash Levy
b5f3d7ee9c Revert three passes 2025-09-29 00:18:34 -07:00
Jannis Harder
cbc1055517 opt_clean: Fix debug output when cleaning up bufnorm cells 2025-09-29 08:21:28 +02:00
Jannis Harder
9396e5e5fe portarcs: Ignore all bufnorm helper cells
The `portarcs` pass was already ignoring `$buf` cells when loading
timing data, but now bufnorm will also emit `$input_port` and `$connect`
helper cells, which need to be ignored as well.
2025-09-29 08:21:28 +02:00
Akash Levy
a0d1c8b30f More minor cleanup 2025-09-28 07:19:53 -07:00
Akash Levy
507d43a9b8 Fixups 2025-09-28 06:16:07 -07:00
Akash Levy
652a9a63b2 Update to latest and fix all disabled tests 2025-09-28 01:33:08 -07:00
Akash Levy
ae2ed5e82a Fix wreduce speed more 2025-09-27 17:59:25 -07:00
Jannis Harder
ce5d04a42f hierarchy: Suggest more specific command to skip unsupported SVA 2025-09-26 18:41:26 +02:00
Akash Levy
f7dbfcb278 Fix wreduce speed issue 2025-09-26 07:55:37 -07:00
KrystalDelusion
7ebd972165
Merge pull request #5277 from YosysHQ/krys/fix_4983_alt
autoname: Avoid integer overflow
2025-09-26 14:11:20 +12:00
Krystine Sherwin
fef6bdae6c
autoname.cc: Return number of renames
Was previously the number of proposed renames, but since renames can be skipped this causes the final count to differ from the number of actually renamed objects.
Check counts in `tests/various/autoname.ys`.
2025-09-26 11:05:50 +12:00
Akash Levy
d704eba595 Fix traceability by reverting to old abc 2025-09-25 10:16:22 -07:00
Emil J
8c8d18f2d8
Merge pull request #5392 from rocallahan/opt-merge-cleanup
Some small readability improvements to `OptMergeWorker`
2025-09-25 12:15:33 +02:00
Martin Povišer
29e0144ebc
Merge pull request #5381 from povik/abc9-multilib
Support multiple lib files in abc9_exe
2025-09-25 09:45:09 +02:00
Robert O'Callahan
4d209c187d Switch OptMergeWorker cell type switching to use IdString::in() 2025-09-25 03:06:58 +00:00
Robert O'Callahan
1c73011e7e Swap SigSpecs using std::swap with moves 2025-09-25 03:04:17 +00:00
Jannis Harder
83dd99efb7 verific: New -sva-continue-on-error import option
This option allows you to process a design that includes unsupported
SVA. Unsupported SVA gets imported as formal cells using 'x inputs and
with the `unsupported_sva` attribute set. This allows you to get a
complete list of defined properties or to check only a supported subset
of properties. To ensure no properties are unintentionally skipped for
actual verification, even in cases where `-sva-continue-on-error` is
used by default to read and inspect a design, `hierarchy -simcheck` and
`hierarchy -smtcheck` (run by SBY) now ensure that no `unsupported_sva`
property cells remain in the design.
2025-09-24 18:58:54 +02:00
Jannis Harder
71882debe7 simplemap: Remove leftover debug output 2025-09-24 13:20:27 +02:00
Jannis Harder
904d49c6d8 abc9_ops: Remove temporary debug log message
I missed this when adding the -replace_zbufs option.
2025-09-24 13:20:27 +02:00
Jannis Harder
7a69dbb63d
Merge pull request #5372 from rocallahan/abc-done
Make ABC_DONE tracking more robust
2025-09-24 08:40:26 +02:00
Robert O'Callahan
e9aacd8a05 Move OptMerge cell filtering logic to happen while building the cell vector.
This code is quite confusing because there are two "is the cell known" filters
applied, one while building the cell vector and one after building the cell
vector, and they're subtly different. I'm preserving the actual behaviour here
but it looks like there is, or was, a bug here.
2025-09-23 23:26:47 +00:00
Emil J
5f6819fd76
Merge pull request #5361 from YosysHQ/emil/simplemap-transfer-src
simplemap: fix src attribute transfer
2025-09-23 20:40:57 +02:00
Martin Povišer
3f4b6dc5d3 Support multiple lib files in abc9_exe 2025-09-23 20:34:08 +02:00
KrystalDelusion
d4071b63f7
Merge pull request #5268 from YosysHQ/krys/cutpoint_inout
Track wire drivers in cutpoint
2025-09-24 04:14:19 +12:00
Akash Levy
cd37b064f9 Minor cleanup 2025-09-23 01:07:41 -07:00
Akash Levy
a3542ae405 Fixup 2025-09-23 00:38:43 -07:00
Robert O'Callahan
1e5f920dbd Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
Akash Levy
5f7361e66b Try fixing ThreadPool issue 2025-09-22 18:50:22 -07:00
Akash Levy
d16ca47549
Merge branch 'YosysHQ:main' into main 2025-09-22 17:47:23 -07:00
Jannis Harder
13a2481da7
Merge pull request #5365 from rocallahan/deterministic-abc
Extract ABC results in the order of `assigned_cells`
2025-09-22 23:21:11 +02:00
Emil J
a78eb9e151
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort
write_rtlil: don't sort
2025-09-22 11:14:39 +02:00
Robert O'Callahan
7f6fae1f66 Extract ABC results in the order of assigned_cells.
Currently the order of extraction can vary based on which ABC runs finish first. That's
nondeterministic, therefore bad. Instead, force the processing to happen in the same order
as `assigned_cells`, i.e. the same order we use when not using parallelism. This should
make everything deterministic.

Note that we still allow ABC runs to complete out of order. Out-of-order results are
just not extracted until all the previous runs have completed and their results
extracted.
2025-09-22 05:07:03 +00:00
Robert O'Callahan
4fc782ef2b Make ABC_DONE detection more robust.
1) Change token from ABC_DONE to YOSYS_ABC_DONE to be a bit more robust against false matches.
2) Emit the token from the sourced script so that we don't have to worry about it showing up in the echoing
of the command as it executes. It will only appear in ABC stdout when it executes, i.e. when
our script has completed.
3) `set abcout` doesn't actually switch ABC to line buffering on stdout, since HAVE_SETVBUF is not actually
set in ABC builds in general. So stop using that. ABC does the necessary flushing when
`source` has finished.
2025-09-22 05:01:51 +00:00
Robert O'Callahan
2de641d051 Don't redirect spawned ABCs' stderr to our pipe.
popen() doesn't do this and we should emulate the behavior of popen() as much as possible.
2025-09-22 05:01:51 +00:00