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Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort

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write_rtlil: don't sort
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Emil J 2025-09-22 11:14:39 +02:00 • committed by GitHub
commit a78eb9e151
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19 changed files with 247 additions and 109 deletions
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2
passes/cmds/bugpoint.cc
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@ -122,8 +122,6 @@ struct BugpointPass : public Pass {
int run_yosys(RTLIL::Design *design, string runner, string yosys_cmd, string yosys_arg, string suffix, bool catch_err)
{
design->sort();
string bugpoint_file = "bugpoint-case";
if (suffix.size())
bugpoint_file += stringf(".%.8s", suffix);

9
passes/techmap/techmap.cc
View file

@ -1032,6 +1032,10 @@ struct TechmapPass : public Pass {
log(" -dont_map <celltype>\n");
log(" leave the given cell type unmapped by ignoring any mapping rules for it\n");
log("\n");
log(" -relativeshare\n");
log(" use paths relative to share directory for source locations\n");
log(" where possible (experimental).\n");
log("\n");
log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
log("match cells with a type that match the text value of this attribute. Otherwise\n");
log("the module name will be used to match the cell. Multiple space-separated cell\n");
@ -1185,6 +1189,11 @@ struct TechmapPass : public Pass {
verilog_frontend += " -I " + args[++argidx];
continue;
}
if (args[argidx] == "-relativeshare") {
verilog_frontend += " -relativeshare";
log_experimental("techmap -relativeshare");
continue;
}
if (args[argidx] == "-assert") {
worker.assert_mode = true;
continue;

2
passes/tests/raise_error.cc
View file

@ -47,7 +47,7 @@ struct RaiseErrorPass : public Pass {
extra_args(args, argidx, design, true);
RTLIL::NamedObject *err_obj = nullptr;
for (auto mod : design->all_selected_modules()) {
if (mod->has_attribute(ID::raise_error)) {
err_obj = mod->clone();